Type Conversions

[Weaam Attallah]

Hi All,

I am writing a VHDL code that uses type conversion functions from std_logic to vl_logic,I have created

the conversions functions properly, the code is as follows:

entity trial is

end trial;

architecture behave of trail is

component verilog_inv

port(

a: inout vl_logic;

b: out vl_logic

)

end component;

......

signal \N$2\ : std_logic;

..

inst : verilog_inv

port map(

to_stdlogic(a) => \N$2\;

......

end behave;

when compiling this code using MODELSIM 5.7 , I got this compilation error:

"Type error in variable \N$2\. Needed type vl_logic."

when I changed port map to "to_stdlogic(a) => to_vllogic(\N$2\);"

it compiled successfully..Does anyone have explanation for this error?

Regards,

Weaam

 

[Paul Uiterlinden]

when I changed port map to "to_stdlogic(a) => to_vllogic(\N$2\);"
it compiled successfully..Does anyone have explanation for this error?

See pages 62 and 63 (starting at line 463) of the 1993 LRM.

In short, you have to supply a conversion function in the data flow
direction.

That means that for IN you must apply the conversion function on the
actual parameter (right hand side), for OUT/BUFFER you must apply the
conversion function on the formal parameter (left hand side).

For INOUT you have to apply conversion functions on both sides, as
data can go in both directions.

Paul.