Martin Maurer skrev:
Hello,
does someone have an UART with an fractional baudrate generator ? Or the
baudrate generator stand alone ? I search examples in VHDL.
Regards,
Martin
Hi,
The baudrate generator could be written according to the example below:
Library ieee;
Use ieee.std_logic_1164.all;
Use ieee.numeric_std.all;
Entity brgrx Is
Port(
clk : In Std_logic;
res : In Std_logic;
clkrx : Out Std_logic
);
End brgrx;
Architecture RTL Of brgrx Is
Signal brdiv : unsigned(8 downto 0); -- Counter
Signal iclkrx : std_logic; -- Internal CLKRX
Signal ubrr : unsigned(8 downto 0); -- div ratio
Signal toggle : std_logic; -- 351/352 control
Begin
-- Division control. Divide by 351 or 352 to get an average of 351,5
divctrl : Process (clk,res)
Begin
if res = '1' then
toggle <= '0';
elsif rising_edge(clk) then
if iclkrx = '1' then
toggle <= not toggle;
end if;
end if;
End process divctrl;
ubrr <= TO_UNSIGNED(351,9) when toggle = '1' else TO_UNSIGNED(350,9);
-- Divide by ubrr+1 i.e 351/352
divider : Process (clk,res)
Begin
if res = '1' then
brdiv <= (others => '0');
iclkrx <= '0';
elsif rising_edge(clk) then
if brdiv = ubrr then
brdiv <= (others => '0');
iclkrx <= '1';
else
brdiv <= brdiv + 1;
iclkrx <= '0';
end if;
end if;
End Process divider;
clkrx <= iclkrx;
End RTL;
Its not necessary to use two processes, they may be combined to a
single process. It would also be possible to make the toggle control
more complex, to accomplish an average divisor of e.g 351,25 or 351,75
(if the jitter is acceptable).
/Peter