Using "others" in if statement

Discussion in 'VHDL' started by Kot, Aug 30, 2003.

  1. Kot

    Kot Guest

    What would be a good way to say "when not all bits are 0's" ?
    I tried :
    if ok_count /= ( others => '0') then
    ....

    also
    if not ( ok_count = ( others => '0') then
    ....

    but I get error message saying :
    aggregate with others must be in a constrained context.

    I think it's context is constrained enough -- ok_count is
    std_logic_vector(11 downto 0)

    I'm using Synplify. Does other tools complains in the same way?

    Jihwan Song
     
    Kot, Aug 30, 2003
    #1
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  2. This would work for an assignment :

    ok_count <= ( others => '0');

    But for a comparison, the compiler doesn't
    know for sure which vector full of zeros you mean.

    All you have to do is clarify which vector you mean:

    if ok_count /= ( ok_count'range => '0') then . . .


    Note that the compiler might have more than one vector to
    consider in more complex comparisons:

    if ok_count /= ( vec1'range => '0') & (vec2'range => '1') then . . .

    -- Mike Treseler
     
    Mike Treseler, Aug 30, 2003
    #2
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  3. Hi,
    You may take a look at Section 4.2.5 (Operations With
    Array Aggregates) of the FAQ:

    http://www.vhdl.org/comp.lang.vhdl/FAQ1.html#const_vectors
     
    Edwin Naroska, Sep 1, 2003
    #3
  4. You had good replies already, but can I suggest two possibilities
    which may be clearer...

    (1) Use the numeric package:

    use ieee.numeric_std.all; -- or std_logic_arith
    ....
    if unsigned(ok_count) /= 0 then ...


    (2) Write a function, for clarity:

    function all_zero(v: std_logic_vector) return boolean is
    begin
    return (v = (v'range => '0'));
    -- or, if you prefer...
    -- for i in v'range loop
    -- if v(i) /= '0' then
    -- return false;
    -- end if;
    -- end loop;
    -- return true;
    end;
    ....
    if not all_zero(ok_count) then ...

    --

    Jonathan Bromley, Consultant

    DOULOS - Developing Design Know-how
    VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project Services

    Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW, UK
    Tel: +44 (0)1425 471223 mail:
    Fax: +44 (0)1425 471573 Web: http://www.doulos.com

    The contents of this message may contain personal views which
    are not the views of Doulos Ltd., unless specifically stated.
     
    Jonathan Bromley, Sep 1, 2003
    #4
  5. (3) Write a function for synthesis using a logarithmic algorithm; it
    could lead to faster hardware implementations:

    function ALL_ZERO(V: Std_Ulogic_Vector) return Std_Ulogic is
    variable T: Std_Ulogic_Vector(V'length - 1 downto 0) := V;
    begin
    case T'length is
    when 0 => return '0';
    when 1 => return T(0);
    when 2 => return T(0) or T(1);
    when others => return ALL_ZERO(T(T'length - 1 downto T'length / 2))
    or ALL_ZERO(T(T'length / 2 - 1 downto 0));
    end case;
    end ALL_ZERO;

    Regards,
     
    Renaud Pacalet, Sep 1, 2003
    #5
  6. Elegant and beautiful in the hands of one as skilled as you, Renaud,
    but (as I'm sure you'll agree) it's not trivially easy to get the
    details right.

    In my experience, serious synthesis tools do quite a good job of
    mapping cascaded logic on to a tree structure when appropriate.
    Developing the tree by hand or by algorithm is often unnecessary.
    --

    Jonathan Bromley, Consultant

    DOULOS - Developing Design Know-how
    VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project Services

    Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW, UK
    Tel: +44 (0)1425 471223 mail:
    Fax: +44 (0)1425 471573 Web: http://www.doulos.com

    The contents of this message may contain personal views which
    are not the views of Doulos Ltd., unless specifically stated.
     
    Jonathan Bromley, Sep 1, 2003
    #6
  7. Thank for the good words, you made my day ;-)
    You're probably right. It could be interesting to compare ac, dc,
    leonardo, and others on this.

    Best regards,
     
    Renaud Pacalet, Sep 1, 2003
    #7
  8. Actually Mr. Pacalet's function works fine using Leo.
    I had a look at the netlist schematic,
    and I don't see how it could be done any cleaner.


    -- Mike Treseler

    ------------------------------------------------------------------
    library ieee;
    use ieee.std_logic_1164.all;

    entity ck_zero is

    generic (len : natural := 64);

    port (a : in std_ulogic_vector(len-1 downto 0);
    clk : in std_ulogic;
    rst : in std_ulogic;
    zero : out std_ulogic);

    end entity ck_zero;

    architecture synth of ck_zero is

    function ALL_ZERO(V : std_ulogic_vector) return std_ulogic is
    -- by Renaud Pacalet
    variable T : std_ulogic_vector(V'length - 1 downto 0) := V;
    begin
    case T'length is
    when 0 => return '0';
    when 1 => return T(0);
    when 2 => return T(0) or T(1);
    when others => return
    ALL_ZERO(T(T'length - 1 downto T'length / 2))
    or ALL_ZERO(T(T'length / 2 - 1 downto 0));
    end case;
    end ALL_ZERO;

    begin
    process (rst, clk) is
    begin -- process
    clked : if rst = '1' then
    zero <= '1';
    elsif rising_edge(clk) then
    zero <= ALL_ZERO(a);
    end if clked;
    end process;

    end architecture synth;



    ***********************************************
    Device Utilization for 2V40cs144
    ***********************************************
    Resource Used Avail Utilization
    -----------------------------------------------
    IOs 67 88 76.14%
    Function Generators 21 512 4.10%
    CLB Slices 11 256 4.30%
    Dffs or Latches 1 776 0.13%
    Block RAMs 0 4 0.00%
    Block Multipliers 0 4 0.00%

    -----------------------------------------------
    Using wire table: xcv2-40-6_wc



    Clock Frequency Report

    Clock : Frequency
     
    Mike Treseler, Sep 2, 2003
    #8
  9. I wrote lots of them. Mostly they follow about this template , so once
    you get the idea it is quite easy.
    (BTW : I guess the 2 case is not strictly necessary , but it doesn't
    hurt especially for readibility.)

    Completely different (although maybe slightly outdated) experience.
    Synthesis tools tend to do OK on an isolated example. They tend
    to fail when this is buried into lots of other logic.


    Regards,

    Jos
     
    Jos De Laender, Sep 2, 2003
    #9
  10. It just speeds up the simulation. On a 2**N bits vector, without the 2
    case you get 2**(N+1) - 1 calls to the function. With the 2 case you get
    2**N - 1 calls, that is, a speed up of about 50%. It may be worth the
    extra line of code. But to be honest, if you really care about
    simulation speed you will simulate with Jonathan's version or something
    similar and - in case your synthesizer is not smart enough - you will
    synthesize with something like mine. So you're right, the 2 case is useless.

    Regards,
     
    Renaud Pacalet, Sep 3, 2003
    #10
  11. Very interesting observation! I didn't look at it that way, but it is
    clear that you're absolutely right.

    But looking at it that way , I have in fact another question/remark.

    Isn't it much more realistic to expect from the _simulator_ that it
    works away the tail recursion into iteration than to expect from the
    _synthesizer_ that it reconstructs a tree from a chain ?
    After all , and as far as my limited compiler knowledge goes , working
    away tail recursion into iteration is a pretty well established
    technique ?

    Best regards ,

    Jos
     
    Jos De Laender, Sep 4, 2003
    #11
  12. Well, I'm not a compiler expert but I would not expect anything so smart
    from my VHDL simulators. And my benchmarks with the most famous
    simulators will not change my mind. Same for the synthesizers: I usually
    don't trust them at all.

    Regards,
     
    Renaud Pacalet, Sep 5, 2003
    #12
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