vector concatenation

Discussion in 'VHDL' started by pandora, Apr 3, 2004.

  1. pandora

    pandora Guest

    hello:
    I am a beginner of vhdl, I have some knowledge about verilog. please
    help me with this problem:
    In VHDL serveral vector can concatenate like " a & b & c " also (a ,b
    ,). i know this can be used as the right operand when assigning. but can
    the concatenated vector be the left operand? i writed like this
    (a,b,c)<= d ; or
    a & & c <= d;
    but all can not pass the compilation.

    can tell me how the cooncatenated vector be the left operand? thanks
    you!!
     
    pandora, Apr 3, 2004
    #1
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  2. pandora

    Niv Guest

    "pandora" <> wrote in message
    news:...
    > hello:
    > I am a beginner of vhdl, I have some knowledge about verilog. please
    > help me with this problem:
    > In VHDL serveral vector can concatenate like " a & b & c " also (a ,b
    > ,). i know this can be used as the right operand when assigning. but can
    > the concatenated vector be the left operand? i writed like this
    > (a,b,c)<= d ; or
    > a & & c <= d;
    > but all can not pass the compilation.
    >
    > can tell me how the cooncatenated vector be the left operand? thanks
    > you!!
    >

    I've not checked, but I don't think you can do this; you have to slice the
    rhs thus:

    a <= d(msb downto X);
    b <= d(X-1 downto Y);
    c <= d(Y-1 downto 0);

    Or something similar.

    Niv.
     
    Niv, Apr 3, 2004
    #2
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  3. "pandora" <> wrote in message
    news:...
    > hello:
    > I am a beginner of vhdl, I have some knowledge about verilog. please
    > help me with this problem:
    > In VHDL serveral vector can concatenate like " a & b & c " also (a ,b
    > ,). i know this can be used as the right operand when assigning. but can
    > the concatenated vector be the left operand? i writed like this
    > (a,b,c)<= d ; or
    > a & & c <= d;
    > but all can not pass the compilation.
    >
    > can tell me how the cooncatenated vector be the left operand? thanks
    > you!!


    Here an example. It would be nice if the line marked with --***
    could be (co,s)<=...
    But that is not allowed (yet).

    Egbert Molenkamp

    LIBRARY ieee;
    USE ieee.numeric_bit.ALL;
    ENTITY adder IS
    PORT (a,b : IN unsigned(1 DOWNTO 0);
    ci : IN bit;
    s : OUT unsigned(1 DOWNTO 0);
    co : OUT bit);
    END adder;
    ARCHITECTURE demo OF adder IS
    BEGIN
    (co,s(1),s(0)) <= ('0'&a) + b + ('0'&ci) ; --***
    END demo;
     
    Egbert Molenkamp, Apr 3, 2004
    #3
  4. pandora

    pandora Guest

    but sometimes the left part is an expression, you can not write like this!
    so it is really troublesome to write every bit in the left when it is a
    very long vector.
     
    pandora, Apr 3, 2004
    #4
  5. Mike Treseler, Apr 4, 2004
    #5
  6. "pandora" <> wrote
    > but sometimes the left part is an expression, you can not write like this!
    > so it is really troublesome to write every bit in the left when it is a
    > very long vector.


    Then use a variable

    my_var:=my_function(x,y,z);
    a<=my_var(t downto s);
    b<=my_var(s-1 downto r);
    c<=my_var(r-1 downto 0);

    bye Thomas
     
    Thomas Stanka, Apr 5, 2004
    #6
  7. pandora

    ZOLVEZ

    Joined:
    Oct 2, 2007
    Messages:
    8
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    0
    hello

    I need some help
    I want to do this:

    tmp<= tmp1(6 downto 4);

    it means I want to use only a part of the vector no all the bits
    so I tried to do that, but de ISE of Xilinx doesn't sinthesize it
    it reports a message like this:
    signal tmp(3 downto 0): is never used

    do you know another way ? Please any suggestions to ZOLVEZ@hotm..
    thanks a lot
     
    ZOLVEZ, Oct 2, 2007
    #7
  8. pandora

    ZOLVEZ

    Joined:
    Oct 2, 2007
    Messages:
    8
    Likes Received:
    0
    hello

    I need some help
    I want to do this:

    A<= tmp1(6 downto 4);

    it means I want to use only a part of the vector no all the bits
    so I tried to do that, but de ISE of Xilinx doesn't sinthesize it
    it reports a message like this:
    signal tmp1(3 downto 0): is never used

    do you know another way ? Please any suggestions to ZOLVEZ@hotm..
    thanks a lot
     
    ZOLVEZ, Oct 2, 2007
    #8
  9. pandora

    vipinlal

    Joined:
    Feb 25, 2010
    Messages:
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    0
    some examples for concatenation operator is available here..
    vhdlguru.blogspot.com/2010/03/concatenation-operator-in-vhdl.html
     
    vipinlal, Mar 26, 2010
    #9
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