hello: I am a beginner of vhdl, I have some knowledge about verilog. please help me with this problem: In VHDL serveral vector can concatenate like " a & b & c " also (a ,b ,). i know this can be used as the right operand when assigning. but can the concatenated vector be the left operand? i writed like this (a,b,c)<= d ; or a & & c <= d; but all can not pass the compilation. can tell me how the cooncatenated vector be the left operand? thanks you!!