hello:\nI am a beginner of vhdl, I have some knowledge about verilog. please\nhelp me with this problem:\nIn VHDL serveral vector can concatenate like " a & b & c " also (a ,b\n,). i know this can be used as the right operand when assigning. but can\nthe concatenated vector be the left operand? i writed like this\n(a,b,c)<= d ; or\na & & c <= d;\nbut all can not pass the compilation.\n\ncan tell me how the cooncatenated vector be the left operand? thanks\nyou!!