Verification by Non-HDL(C++/Java)??

Discussion in 'VHDL' started by Davy, May 10, 2006.

  1. Davy

    Davy Guest

    Hi all,

    I found that some verification procedure using Non-HDL such as
    C++/Java.

    But how these Non-HDL language generate edge stimulus? Can Non-HDL also
    generate @posedage???

    Is there any basic idea behind it?

    Best regards,
    Davy
     
    Davy, May 10, 2006
    #1
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  2. Davy

    naren Guest

    Hi Davy,
    They do it through an interface called VHPI (for VHDL) or PLI (for
    verilog). A quick googling should give you decent links.
    You could also write t/b's in perl / python et.al...
    Thanks,
    Naren.
     
    naren, May 10, 2006
    #2
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  3. Davy

    Hans Guest

    and you might also want to look at SystemC which, IMHO, is easier to
    interface to Verilog/VHDL.

    Hans
    www.ht-lab.com
     
    Hans, May 10, 2006
    #3
  4. Srinivasan Venkataramanan, May 11, 2006
    #4
  5. Davy

    mmintz Guest

    Hi Davy,

    I am the creator to teal. Let me know if I can help in any way.

    I am also real close to releasing a verification framework in C++.

    Take Care,
    Mike
     
    mmintz, May 11, 2006
    #5
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