Hi,\nI want to know basic about verification. I know VHDL lang. I am working\non a project in VLSI. I worked on xilinx webpack6.8, modelsim 5.8 &\nleonardo spectrum.\nNow i got a call for interview... which is for verification engineer.\nplease guide me what should I know about verification as I am preparing\nfor that. give me some general questions with hint answers.