Verilog (include) to VHDL (....) problem

Discussion in 'VHDL' started by Luc, Jul 26, 2004.

  1. Luc

    Luc Guest


    I have a reference design in Verilog, that I'm translating in VHDL.
    The problem is that the Verilog design uses 'include files to load
    some parameters.
    If it were real numbers, I guess this won't be a big issue as one can
    use CONSTANT .... in stead.
    The problem is that the Verilog file uses a form like

    parameter CLK_WAIT = (CLK_tPD <3) ? 0 : CLK_tPD - 3);

    translating in something like :
    if( CLK-tPD < 3) then 0 ELSE (CLK-tPD -3)

    but as far as I know this can't be done in VHDL, simple
    multiplications or divisions yes, but decisive ... I don't know

    Any Ideas are much apreciated

    Best regards,

    Luc, Jul 26, 2004
    1. Advertisements

  2. This is a fault in VHDL that will (may?) be fixed in the next revision
    (when you will be able to type:

    constant CLK_WAIT = 0 when CLK_tPD < 3 else CLK_tPD - 3;

    ). In the meantime, you can create a function:

    pure function make_CLK_WAIT returns integer is
    if( CLK-tPD < 3) then
    return 0;
    return (CLK-tPD -3);
    end if;
    end make_CLK_WAIT;

    constant CLK_WAIT = make_CLK_WAIT();

    Allan Herriman, Jul 26, 2004
    1. Advertisements

  3. Uuurgh. I've been using Verilog too much recently. That should have

    constant CLK_WAIT : integer := make_CLK_WAIT();

    Allan Herriman, Jul 26, 2004
  4. It's an occupational hazard :)

    The OP's question set me thinking, though: lack of the
    conditional ?: operator in VHDL-93 is a tad irritating.
    So let's fix it...

    function expr_if (
    condition : boolean;
    value_if_true : integer;
    value_if_false : integer
    ) return integer is
    if condition then
    return value_if_true;
    return value_if_false;
    end if;

    and then overload to your heart's content for all sorts
    of other data types.

    Then we can say

    constant CLK_WAIT: integer :=
    expr_if( CLK_tPD < 3, 0 , CLK_tPD - 3);

    Sheesh, we're starting to make it look just like Excel :-(

    Don't even think about type templates/generics.
    Jonathan Bromley, Consultant

    DOULOS - Developing Design Know-how
    VHDL, Verilog, SystemC, Perl, Tcl/Tk, Verification, Project Services

    Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, BH24 1AW, UK
    Tel: +44 (0)1425 471223 mail:
    Fax: +44 (0)1425 471573 Web:

    The contents of this message may contain personal views which
    are not the views of Doulos Ltd., unless specifically stated.
    Jonathan Bromley, Jul 26, 2004
  5. Allan Herriman, Jul 26, 2004
  6. Luc

    Luc Guest


    Thanks all that replied so far. Indeed a conditional operator is
    missing in VHDL. I missed it a couple of times in generics.
    In Verilog, one can easily do this by using include.
    The proposed solutions are still workaround (I can live with that,
    that's not the point).

    Jonathan, have you thought about nested conditions, something like
    if1st_condition then
    if 2nd_condition then
    return 2nd_value;
    if 3th_condition then
    return 3th_value;
    return default_value;
    end if;
    Then implemented like
    expr_if(CLK_tPD < 3, 0, expr_if(CLK_tPD>12, 10, CLK_tPD - 3));

    Is this feasable? This realy looks like MS-Excel, ...
    And then you have to overload to other types ... mmmh!?!

    Luc, Jul 26, 2004
  7. Luc

    Jim Lewis Guest

    What you want is FT10A:

    I split them out into separate items. FT10B is
    good for lanugage consistency across concurrent
    and sequential statements, however, in light of
    FT10A, I am thinking that I will always use
    the proposed n-nary expressions and never again use
    the format of conditional signal assignment.
    So that leads me to, should we do FT10B or not?
    When we ask vendors for more features, we need to
    make sure we can justify them by using them.

    Note for FT10A, I orignally tried to make the syntax
    work in a way that it would be identical to conditional
    signal assignment. It is not possible to achieve the
    consistency I wanted, so we came up with a different


    Jim Lewis
    Director of Training mailto:
    SynthWorks Design Inc.

    Expert VHDL Training for Hardware Design and Verification
    Jim Lewis, Jul 31, 2004
    1. Advertisements

Ask a Question

Want to reply to this thread or ask your own question?

You'll need to choose a username for the site, which only take a couple of moments (here). After that, you can post your question and our members will help you out.