verilog module instantantiation in VHDL top level

Discussion in 'VHDL' started by praveen.kantharajapura, Jul 11, 2005.

  1. Hi all,

    In my design all the modules are in VHDL except one which is in
    verilog.I wanted to know if it is possible to call my verilog module in
    my VHDL top level.

    If possible can any body tell me how to go about it.

    Regards,
    Praveen
     
    praveen.kantharajapura, Jul 11, 2005
    #1
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  2. praveen.kantharajapura

    Tarun Batra Guest

    Hi Praveen,
    You will have to create a wrapper for the Verilog model as:

    Entity <module name> is
    End <module name>;

    architecture verilog of <name> is
    attribute foreign of verilog:architecture is "VERILOG(event)
    work.<module name>:modulel";
    begin
    end;

    In case you are using NCSIM, you can directly instantiate the verilog
    component in VHDL.
    NCSIM allows the instantiation of the Verilog in VHDL either through
    direct instantiation, component binding or default bindings.

    -Tarun
     
    Tarun Batra, Jul 11, 2005
    #2
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