Verilog/VHDL Simulation

Discussion in 'VHDL' started by Elf, Oct 10, 2003.

  1. Elf

    Elf Guest

    Hi,

    Can anyone tell me if the netlist generated by a simulator is language
    specific or not...
    like for eg. I generate code for the "same design" in both Verilog and
    in VHDL and then simulate them using a single simulator, will the
    netlist thats generated be the same..?
    One may say Yes, coz ultimately what the simulator is doing is
    generating "assembly language instructions" based on the design code,
    so they shd be independent of the HDL....

    But then I have seen studies where the code for similar Verilog and
    VHDL designs had different number of code lines, and differnt no. of
    "partitions(always block/process block)...and this might result in a
    slightly diffenrt netlist being generated....

    regards,
    Elf.
     
    Elf, Oct 10, 2003
    #1
    1. Advertisements

  2. Synthesis generates a netlist.
    Simulation generates a binary version of the source code
    optimized for speed.

    I would be surprised if either were identical for
    vhdl and verilog versions of the same design.
    The best way to answer this question is to
    try it for a simple example.

    -- Mike Treseler
     
    Mike Treseler, Oct 10, 2003
    #2
    1. Advertisements

Ask a Question

Want to reply to this thread or ask your own question?

You'll need to choose a username for the site, which only take a couple of moments (here). After that, you can post your question and our members will help you out.