I'm defining a component with some generic constants in VHDL. I'd like
to make synthesis fail with an error if the value given to one of the
constants doesn't satisfy some conditions. Is there any way to do this?
The way I check the consistency of generics with each other or with design
assumptions is:
entity ClkPrescaler
is generic (gPrescalerlength : integer := 2;
gPrescalerValue : integer := 1;
...)
port (...);
end ClkPrescaler;
architecture synthesisable of ClkPrescaler
is
subtype tPrescaler is Unsigned (gPrescalerLength-1 downto 0);
constant cPrescalerMaximum : tPrescaler :=
to_unsigned(2**gPrescalerlength-1, gPrescalerLength);
...
begin
...
assert 1 <= gPrescalerValue and gPrescalerValue <= cPrescalerMaximum
report "gPrescalerValue (" & integer'image(gPrescalerValue)
& ") is out of range : 1..2**gPrescalerLength-1 ("
& integer'image(to_integer(cPrescalerMaximum)) & ")"
severity Failure;
...
end synthesisable;
HTH
If you wish to clean up the function soup used to generate integer text,
define some functions.
Sadly, I don't know of a better way - but live in hope of enlightenment.
I know from experience that the above assertion will fire in ModelSim,
Synplicity and LeonardoSpectrum.
However, the assertion doesn't always work in Xilinx XST; based on back to
back testing with ModelSim. gPrescalerValue = 0 -> assertion raised, =
16 -> assertion not raised (erroneous behaviour). Additionally, XST doesn't
output the fancy messages; you get "Assert statement with non static report"
substituted for the error message; so you stick to dumb text. (I'll open a
case with Xilinx regarding these issues; caveat XST).
A broader issue raised, by this and other 'experiences' with tools, is to
question whether it is not time that VHDL grew some
verification/certification test suites (like Ada and C) and if necessary
standardised implementation subsets to define/verify which language features
have been implemented by a tool.
Martin