VHDL for verification

[Shiladitya]

Dear All,

the assertion based verification methodology gaining more
popularity, and VHDL not providing enough features related to
assertions,
I think ts really a matter of concern. Whats your opinion on the
SystemC & SystemVerilog gaining more popularity than VHDL in
verification and transaction level modelling?

Regards,
Shiladitya.

 

[Allan Herriman]

Dear All,

the assertion based verification methodology gaining more
popularity, and VHDL not providing enough features related to
assertions,

What features do you think it lacks?

Allan.

 

[Srinivasan Venkataramanan]

Hi,
There is already a working group set up to handle this, see
http://www.eda.org/vhdl-200x/vhdl-200x-asr/

From my view point, PSL will be the standard assertion language and tools
will eventually start supporting it (I know that Cadence, @HDL, Modelsim -
with Safelogic PLI, Aldec's Riveria already support it). For PSL, you may
want to check out Ben Cohen's book, see http://www.vhdlcohen.com

Srinivasan

--
Srinivasan Venkataramanan
Senior Verification Engineer
Software & Silicon Systems India Pvt Ltd. - an Intel company
Bangalore, India

http://www.noveldv.com http://www.deeps.org

I don't speak for Intel

 

[Shiladitya]

Dear Allan,

What features do you think it lacks?

I think that the timing based assertions, are missing in VHDL. Not
only that the H/W S/W co-verification concept is missing. Till date
only the functional assertions are possible. There is no way for
checking the race conditions using VHDL alone. For transaction level
modelling too I think some features are lacking.

 

[Jonathan Bromley]

I think that the timing based assertions, are missing in VHDL.

VHDL has no temporal syntax like PSL's or e's, so it is certainly
more difficult to write complicated timing assertions in VHDL
than in those languages. However, there is no difficulty in
principle. VHDL has many useful signal attributes such as
'LAST_VALUE and 'STABLE that make it easy to write simple
timing assertions, and possible to write more complex ones.

Have you investigated the Open Verification Library (OVL)?

the H/W S/W co-verification concept is missing.

If by this you mean that VHDL lacks a standardised interface
to other languages, so that you can create your own co-verification
environment, then you are right. However, many tool vendors have
solutions to this problem for their own VHDL simulators, and there
is a standardisation effort in progress for the VHPI (VHDL's
version of Verilog's PLI).

only the functional assertions are possible.

As I have pointed out above, this is untrue.

There is no way for
checking the race conditions using VHDL alone.

I don't understand exactly what you mean by this.
Do you mean "checking that setup and hold times
are not violated"? That's very easy in VHDL.
If you mean checking for race conditions within the
VHDL code, then that is a well-understood problem of
concurrent programming and VHDL has perfectly adequate
solutions to it.

For transaction level
modelling too I think some features are lacking.

This is definitely true; for TLM it is almost essential
to have some kind of object-oriented language. No doubt this
is why C++ is the language of choice for many TLM efforts
such as SystemC channels.

~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

I am not sure I understand the point of your comments.
Although VHDL can do some things that you say it can't,
it is definitely true that VHDL lacks facilities that
are considered important in modern programming and
verification practice. Either VHDL will evolve to add
those facilities, or it will slowly wither away as have
so many other excellent programming languages. (Who
now uses Pascal, BCPL, Algol-68, POP-II?) There is
excellent work in progress towards "VHDL-200x" -
check it out at www.eda.org

In summary: For timing assertions, get a tool that allows
you to use PSL together with VHDL. For transaction level
modelling, use SystemC - but don't forget that you can
integrate your SystemC and VHDL code into a single simulation,
with some tools. The industry is rapidly developing new
tools and languages to meet new challenges. It seems a bit
unfair to criticise VHDL for failing to answer questions that
simply weren't asked in the mid-80s when it was created.
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project Services

Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW, UK
Tel: +44 (0)1425 471223 mail: (e-mail address removed)
Fax: +44 (0)1425 471573 Web: http://www.doulos.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.

 

[Jim Lewis]

For transaction level modelling too I think some

features are lacking.

Again what is VHDL lacking? Also what does SystemC
and SystemVerilog have that VHDL doesn't?

I have found that transaction level modeling is fairly
straight forward. The easy way to do this is to do
all communications through records. Ben Cohen's books
show how to do this with two separate records (one for
in and one for out). In our VHDL training classes
(http://www.synthworks.com/vhdl_testbench_verification.htm)
we show you how to do it with a single record.

For some details on how to do this, see my DesignCon paper,
Accelerating Verification Through Pre-Use of System-Level Testbench Components
at http://www.synthworks.com/papers.

There are some features on my wish list, but these are
strictly incremental improvements.

Dear All,

the assertion based verification methodology gaining more
popularity, and VHDL not providing enough features related to
assertions,
I think ts really a matter of concern. Whats your opinion on the
SystemC & SystemVerilog gaining more popularity than VHDL in
verification and transaction level modelling?

Regards,
Shiladitya.

--
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Jim Lewis
Director of Training mailto:[email protected]
SynthWorks Design Inc. http://www.SynthWorks.com
1-503-590-4787

Expert VHDL Training for Hardware Design and Verification
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

 

[Jim Lewis]

You have been listening to much to the SystemVerilog
propaganda. The VHDL standards groups are active
and working on a multi-year phased update to VHDL.
All of the good things planned for SystemVerilog will
more than likely also be included in VHDL. However
note with VHDL we have a great stable base to build
from (no race conditions ) and we don't have to mess
with the scheduling algorithms to make the new features
work correctly.

Check out: http://www.eda.org/vhdl-200x
If you don't see the features that you want there,
make sure to request what you want.

Currently SystemVerilog is making it sound like they
are the replacement for both VHDL and Verilog. This
is silly. There are many fundamental differences between
VHDL and Verilog. Syntax wise they are different languages
and they are not converging. Usage wise, VHDL requires you
to learn about strong typing, a feature much like an
assertion check for expression correctness. SystemVerilog
is not adopting strong typing at the bit level (because
it is too difficult for designers to learn the
5-10 simple rules of expressions). Note companies with
advanced Verilog methodologies are using lint tools to
enforce VHDL's strong typing rules and have found that
more than 70% of the time a strong typing violation was
a bug.

Look for consistency through out VHDL and you will find it.
Look for consistency in Verilog, it is not there.
VHDL was touted as bad because strong typing is too
difficult. If you are considering adding assertions to
your code, do you really believe that strong typing is bad?
(that thought makes me giggle ).

With SystemVerilog, you will still need to learn
about Verilog's race conditions and the ad-hoc rules
for when it is appropriate to use blocking vs
non-blocking assignments. Even noted designers
make mistakes with these rules.

Cheers,
Jim
--
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Jim Lewis
Director of Training mailto:[email protected]
SynthWorks Design Inc. http://www.SynthWorks.com
1-503-590-4787

Expert VHDL Training for Hardware Design and Verification
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

 

[Jim Lewis]

With respect to assertions, VHDL is following the
path of SystemVerilog and is basing the temporal assertions
on PSL. There will be a VHDL flavor to it, just like
SystemVerilog has a Verilog flavor to PSL.

Note though, VHDL has always been able to do temporal
assertions. The process with wait statements is a
simple way to do these type of things and for most
practical things is more than enough.

What PSL does do is simplify the expression of the
temporal relationships. Kind of like a one line
statemachine.

For assertions today, check out OVL at
http://www.verificationlib.org/

You mentioned SystemC. Does SystemC provide any type
of assertions?

Cheers,
Jim
--
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Jim Lewis
Director of Training mailto:[email protected]
SynthWorks Design Inc. http://www.SynthWorks.com
1-503-590-4787

Expert VHDL Training for Hardware Design and Verification
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

 

[Jonathan Bromley]

You [Shiladitya] mentioned SystemC. Does SystemC provide
any type of assertions?

SystemC Verification Library (SCV) is "on the case" for such
things, I think. Even as we speak, some of my colleagues
are losing hair and sleep in the process of understanding it
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project Services

Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW, UK
Tel: +44 (0)1425 471223 mail: (e-mail address removed)
Fax: +44 (0)1425 471573 Web: http://www.doulos.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.