VHDL powerup reset module for Altera FPGA

Discussion in 'VHDL' started by lsha, Jun 11, 2004.

  1. lsha

    lsha Guest

    Hi,
    I seem to remember there is a VHDL entity for Xilinx FPGA for powerup
    reset. Is there a similar code for Altera?

    Right now I am using the following process to reset the Altera Cyclone
    chip. But this would generate a huge fanout from nReset, which goes to all
    F/Fs.

    process(Clk)
    begin
    if Clk'event and Clk = '1' then
    if nReset = '0' then
    powerOn <= powerOn + '1';
    end if;
    nReset <= powerOn(3);
    end if;
    end process;

    I know for FPGA once powerup configuration is done the chip is eccentially
    in a known state but since all my clocked process has this structure for
    easy simulation reset:

    if nReset = '0' then
    -- reset
    elsif clk'event and clk = '1' then
    -- work
    end if;

    I need something physical in the chip to do the same thing.

    Thanks in advance.
    lsha
     
    lsha, Jun 11, 2004
    #1
    1. Advertisements

Want to reply to this thread or ask your own question?

You'll need to choose a username for the site, which only take a couple of moments (here). After that, you can post your question and our members will help you out.
Similar Threads
  1. pandora
    Replies:
    0
    Views:
    737
    pandora
    Apr 14, 2004
  2. underground
    Replies:
    5
    Views:
    4,757
    underground
    Jul 22, 2004
  3. Michele Bergo

    EPP interface using Altera FPGA

    Michele Bergo, Nov 5, 2004, in forum: VHDL
    Replies:
    4
    Views:
    1,321
    Mike Treseler
    Nov 26, 2004
  4. john

    CPLD Powerup RESET

    john, Aug 29, 2005, in forum: VHDL
    Replies:
    1
    Views:
    822
  5. sarah
    Replies:
    1
    Views:
    1,280
    Jim Fischer
    Aug 17, 2003
  6. sarah
    Replies:
    11
    Views:
    1,940
  7. chaitu
    Replies:
    1
    Views:
    1,117
  8. Vikram
    Replies:
    0
    Views:
    1,684
    Vikram
    Jul 24, 2008
Loading...