VHDL project

[eman hanoun]

hey guys,
i need ur help in my project realy i dont know how to start and how to combine
plz i will put it and im waiting ur replay if u can
thx in advanced



Overview
In this project you will build a simple part of a microprocessor. Firstly you will build two main blocks: the ALU and the register file, then you will connect them together and run a simple machine code program on them.

In order to ensure that your design is individual to you, various aspects of the design will be dictated by your student ID number. These include the machine code used by your design, the contents of the register file, and the purpose of the program that you will use to demonstrate the correctness of your design. This means that every student should have a unique design.

You have to work individually in this project and demonstrate your work to me and submit a report about your design and implementation of this assignment.


Part 1

The ALU
Write a VHDL description of an ALU with two 32-bit inputs, A and B, and a 32-bit output Result.




The result is derived from one or both of the inputs according to the value of a 6-bit opcode. The operations that the ALU can perform are listed below:
• a + b
• a - b
• |a| (i.e. the absolute value of a)
• -a
• |b| (i.e. the absolute value of b)
• -b
• a or b
• not a
• not b
• a and b
• a xor b

The opcode that will be used to represent each of these operations is determined by the last digit of your student ID number. The table below shows which opcode you should use in your design for each instruction.

Digit of ID no. 0 1 2 3 4 5 6 7 8 9
a + b 15 8 15 9 2 8 9 11 8 15
a – b 10 1 8 1 7 11 6 12 15 11
|a| 1 6 2 3 14 10 15 14 5 10
-a 8 2 3 13 1 9 10 13 10 8
|b| 12 4 11 5 15 15 8 8 14 6
-b 11 12 5 2 3 2 11 7 3 3
a or b 5 14 10 15 9 14 5 3 6 5
not a 7 11 12 4 4 6 12 15 11 1
not b 3 10 6 10 8 7 2 4 9 14
a and b 6 5 4 12 5 3 13 10 1 2
a xor b 9 7 14 6 12 4 1 5 4 13


So, for example, if the last digit of your ID number is 2, then a+b is to be represented by opcode 15, a-b is to be represented by opcode 8, |a| is to be represented by opcode 2 and so on. (These are shown as denary values; your design will of course have to use binary or hexadecimal values.)










The register file

Inside a modern processor there is a very small amount of memory that is used to hold the operands that it is presently working on. This is called the register file, and normally has the following appearance.





This is a very small fast RAM, typically holding 32 x 32-bit words, and therefore requiring a 5-bit address to select out one of the 32-bit words. It is unlike normal RAM in that it can process three addresses at the same time, two of which are always read operations, and one of which is always written to.

Output 1 produces the item within the register file that is address by Address 1. Similarly Output 2 produces the item within the register file that is address by Address 2. Input is used to supply a value that is written into the location addressed by Address 3.

The initial values stored in the register file are determined by the second-from-last digit of your student ID, and are shown in the table below:














ID/
Location 0 1 2 3 4 5 6 7 8 9
0 0 0 0 0 0 0 0 0 0 0
1 7942 11661 12641 12995 4197 11930 4615 15034 5985 16302
2 13224 11562 10591 11490 5596 5348 11649 8854 12259 2994
3 15461 15339 6230 7079 14426 7307 11253 179 482 1658
4 8026 9594 8949 6026 7611 15684 6786 7225 14245 5473
5 7809 15060 10650 10027 7473 4883 8977 11855 4820 14881
6 9882 3287 9436 10344 10040 9715 12431 8928 1847 10835
7 8248 5931 3056 6733 3939 7820 13548 7301 5260 4648
8 3431 1977 4859 15833 4150 5190 13461 8921 16179 523
9 178 4911 3405 15314 6406 14702 13454 1044 4766 12200
10 8079 1664 5303 1400 8434 8210 14267 7074 14928 5396
11 8301 1926 547 12195 8572 2351 13179 258 619 14734
12 591 12725 13053 11290 16323 15423 2982 7354 15105 10997
13 7430 176 2809 13359 8849 2670 8096 3294 9794 4420
14 10572 8407 12988 2086 8258 4171 514 14740 7455 8754
15 14767 5463 1940 6840 10796 5843 3350 6499 9728 1924
16 1238 13604 2193 7439 8462 4744 10870 10436 9309 9049
17 16007 10221 11914 14101 13284 1285 12527 11900 12314 8714
18 2426 7262 15864 13209 4675 8122 9860 14694 12805 12007
19 11939 10199 11832 3264 3989 4558 6166 8839 10477 1005
20 7913 1033 2642 15072 14026 9209 6547 4598 1058 7802
21 12790 12431 2191 15845 7632 13349 14436 4532 6778 12746
22 4841 8723 1849 11719 9845 6917 12135 9083 8430 5461
23 7108 5412 13995 14735 5441 11700 5134 13838 5700 11810
24 6296 11082 12054 5338 12487 10722 11957 10017 13422 7590
25 11333 1639 3710 12405 12661 12691 5413 15642 13067 6519
26 10848 6187 12152 1851 831 3309 5258 5814 1990 10358
27 14698 7056 9875 3898 4664 2385 12420 670 921 15252
28 16378 3743 8733 16251 6798 11212 3569 8832 6020 11953
29 15456 5765 8308 1048 14166 3504 1248 15186 15768 13704
30 7523 10033 15654 7617 4476 15265 15915 8810 6093 12656
31 0 0 0 0 0 0 0 0 0 0

So, for example, if your students ID is 1060381 then the second-from-last digit of your ID number is 8; so item 0 should be 0, item 1 should be 5985, item 2 should be 12259, and so on. (N.B. these values are in denary (i.e. base 10). You will need to convert them to binary or hexadecimal.)

 

[Ukanbal]

okay first of all you have to get your opcodes out according to your student number and i dont know what kind of numbering system your project requires but you might wanna change all those numbers into hexadecimal.

writing the code for ALU
your ALU is basically a bunch of IF statements according to the input opcode.
your ALU portmap is going to be something like this

Port(
A : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
B : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
Clk : IN STD_LOGIC;
select : IN STD_LOGIC_VECTOR (5 DOWNTO 0); ---this is 5 downto 0 because u have an opcode of 6 bits
Q : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
cout : BUFFER STD_LOGIC;
zero : BUFFER STD_LOGIC);

from there the rest is just bunch of if statments like

IF select = "000001" THEN -lets assume this is AND
Q <= (A AND B);
ELSIF select = "000011" THEN -lets assume thats OR
Q <= (A OR B);

and so fort.

register file is a bit tricky. you require 32 registers each 32 bits.
your selecting signal is going to be 5 bits to be able to select which register you want to use. the tricky part of this is the register file has a lot of signals. Your reading operations is asynchronous which means doesnt require the clock signal to operate on the other hand your write signal which allows you to write a value to the specified register is synchronous.
your port of register file is going to be something like
PORT(
clr_RF : IN std_logic;
wen_RF : IN std_logic;
wAdd1 : IN STD_LOGIC_VECTOR(4 downto 0);
rAdd1 : IN STD_LOGIC_VECTOR(4 downto 0);
rAdd2 : IN STD_LOGIC_VECTOR(4 downto 0);
wdata : IN STD_LOGIC_VECTOR(31 downto 0);
rData1 : OUT STD_LOGIC_VECTOR(31 downto 0);
rData2 : OUT STD_LOGIC_VECTOR(31 downto 0);
clk : IN std_logic;
rch0,rch1,rch2,rch3 : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
rch4,rch5,rch6,rch7 : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
rch8... this goes until 31

also you are going to use 32 signals each 32 bit to represent those registers inside the registerfile.

I hope it helps. Good luck

 

[eman hanoun]

hiii

thx very much

but i need to ask u if u can what r u meant by the last three lines in register file??
realy i didnt undestand it!!
and now how can i start to connect both of these ALU and Register file with other??
can i send to u the remaining part of project to help me??
plz
thx in advanced
regards;
eman hanoun

 

[eman hanoun]

Part 2

In this part you will connect the ALU with the RAM to form a simple microprocessor.


Clocking the register file

The register file that you created in the first part was a combinational circuit. This causes some serious problems if, for example, address 2 and address 3 are the same. The circuit would read output 2 from the location referenced by address 2, at the same time that the input is over-writing that location.

These problems can be solved by synchronising the register file to a clock. You will need to add an extra input named clock, and give the register file the following behaviour:

On the rising edge of the clock:
• Output 1 produces the item within the register file that is address by Address 1.
• Output 2 produces the item within the register file that is address by Address 2.
• Input is used to supply a value that is written into the location addressed by Address 3.

Under all other circumstances:
• the outputs are held constant at the values they assumed during the last rising edge of the clock.

You should check your design thoroughly, and in particular make sure that it behaves sensibly when the address for the input is the same as the address of one of the outputs.

Enabling the register file

The register file that you created is always sensitive to its inputs, even when the inputs have garbage values. This can cause problems because when the simulation initializes (which corresponds to the real hardware being switched on) all the values of the logic signals initializes to some random garbage value (denoted ‘U’ in VHDL, but in real life either a ‘1’ or a ‘0’ chosen at random).

Give the register file an enable input. When the enable input=1 the register file will operate normally. Otherwise the register file will ignore its inputs, and will not update its outputs.


Creating the core of the microprocessor

Now create a testbench that contains an instance of the register file and an instance of the ALU connected like this:



Machine instructions are supplied to this arrangement in the form of 32-bit numbers. The format of these instructions is as follows:
• The first 6 bits identify the opcode
• The next 5 bits identify first source register
• The next 5 bits identify second source register
• The next 5 bits identify destination register
• The final 11 bits are unused

So, for example, if you want to add the contents of register 1 and register 2 and put the result into register 3, then the machine instruction would be as follows:
• The first 6 bits supply the opcode for the add instruction
• The next 5 bits would address register 1, and the next 5 would address register 2
• The next 5 bits address register 3.
• The remaining bits are unused, and should be set to zero.

The enable signal to the register should go high when the opcode contains a valid value, and should be low otherwise.

Test out your design by supplying machine instructions to it, and check that the operation performed is correct. Make sure you understand the timing of instructions, and in particular the relationship between the clock cycle on which the instruction occurs, and the clock cycle on which the appropriate result is written to register.




Running a program

Now create a stream of machine instructions that will act as a small program. The program must act as follows:

If the third-form-last digit of your student ID is 1, 4 or 7:
The values stored in the odd-numbered registers (1, 3, 5 … 29) should be added, and the values in the even-numbered registers (2, 4, 6 … 30) should be subtracted to form a total that is written into register 31. The values of registers 1-30 should not be altered by your program, but the value of register 0 may be over-written if you wish.

If the third-form-last digit of your student ID is 2, 5 or 8:
The numbers in registers 1-15 should be added and the values in registers 16-30 subtracted to form a total that is written into register 31. The values of registers 1-30 should not be altered by your program, but the value of register 0 may be over-written if you wish.

If the third-form-last digit of your student ID is 0, 3, 6 or 9:
The values stored in the even-numbered registers (2, 4, 6 … 30) should be added, and the values in the odd-numbered (1, 3, 5 … 29) registers should be subtracted to form a total that is written into register 31. The values of registers 1-30 should not be altered by your program, but the value of register 0 may be over-written if you wish.
You should try to make your program as efficient as possible.

Synchronising the data

All parts of the design that are synchronized to the clock should use only the rising edge of the clock. If you use both the rising edge and the falling edge, then it’s much easier to do the design in simulation, but the real life hardware would be very expensive and complicated to manufacture. You will therefore lose a substantial number of marks if you use both edges of the clock.
One of the main challenges in this design is figuring out on which clock cycle inputs should arrive, and outputs should become valid. If you find that you need to insert registers into some parts of the datapath to get good synchronisation, feel free to do so.

No ops
You may find it useful to create a no-op instruction, i.e. an instruction that instructs the microprocessor to “do nothing” for the next clock cycle, and allocate one of your un-used opcodes to this instruction.

 

[eman hanoun]

plzzzz i need ur help if u can this is the remaining part and the due date 28/4
and i dnt have any idea
thx
regards;
eman hanoun