VHDL RTL description

[Zyd]

Hi,

I am new to this HDL, need some explaination on RTL description. What
is the relation/difference between RTL with
behaviour/structural/dataflow description. I am going to write VHDL to
design MBIST controller that occupy low area overhead and fast
performance. Please give me some advice/ reference regarding this.

Thanks,
Zyd

 

[H. Li]

MBIST? you mean Memory BIST?