VHDL -- Some sort of array of std_logic_vectors ?

[springer54]

So for school I need to make a 2-way set associative cache with a
write-back policy and LRU replacement policy.

it's an 8 lines per way and each way is 8 16-bit words.

Thus, I need 9 bits of tag data, etc.

My question is, well, let's take the tag data for example.

I don't want to have 16 9-bit registers to hold the tag data. Such a
design would be a mess to manage when I make the control unit.

Instead, I would like to have 2 boxes each holding 8 9-bit values which
can be written into and read out of via selecting the right set.

The trouble is, I go to such a good engineering school (top 5), they
seem to believe that they don't actually need to teach VHDL or the
design tools. Nah, we can figure those out on our own.

I liken this to teaching the concept of Red-Black trees and then having
them say, "go write a program that implements them!" without them
having actually taught basic structures in code (not to mention a
programming language)...

Anyway, any help would be appreciated. I *think* what I'm asking about
is pretty basic. But I haven't a clue!

Thanks!

 

[Neo]

well, here is two boxes of 8registers with 9 bits each which can be
read and written into.
----CODE------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity xyz is
port(
clk: in std_logic;
din: in std_logic_vector(8 downto 0);
add: in std_logic_vector(3 downto 0);
rdwr: in std_logic;
do : inout std_logic_vector(8 downto 0)
);
end entity;

architecture acrh_xyz of xyz is
type tag_array1 is array (0 to 7) of std_logic_vector(8 downto 0);
type tag_array2 is array (0 to 7) of std_logic_vector(8 downto 0);

signal tag1: tag_array1;
signal tag2: tag_array2;
begin

--reading
do <= tag1(conv_integer(add(2 downto 0))) when (add(3) = '0' and rdwr =
'0') else
tag2(conv_integer(add(2 downto 0))) when (add(3) = '1' and rdwr =
'0') else
(others => 'Z');

--writing
process(clk)
begin
if(clk'event and clk= '1') then
if(rdwr = '1') then
if(add(3) = '0') then
tag1(conv_integer(add(2 downto 0))) <= do;
else
tag2(conv_integer(add(2 downto 0))) <= do;
end if;
end if;
end if;
end process;

end acrh_xyz;

 

[KCL]

As the two box are the same size you vcould only declare 1 type tag and use
it both for your two signal tag

 

[Mike Treseler]

So for school I need to make a 2-way set associative cache with a
write-back policy and LRU replacement policy.
The trouble is, I go to such a good engineering school (top 5), they
seem to believe that they don't actually need to teach VHDL or the
design tools. Nah, we can figure those out on our own.

Sounds like you're in an upper level class
that requires working knowledge of an HDL.

I liken this to teaching the concept of Red-Black trees and then having
them say, "go write a program that implements them!" without them
having actually taught basic structures in code (not to mention a
programming language)...

I would hesitate to take an algorithms class
without working knowledge of some programming language.

Anyway, any help would be appreciated. I *think* what I'm asking about
is pretty basic. But I haven't a clue!

Consider getting a tutor or dropping the class.

-- Mike Treseler

 

[springer54]

Though it would be nice to drop the class, it is quite important to me.

And I too would hesitate to take an algorishms class without working
knowledge of some, but as far as my problem goes, that is just the way
things are done here.

This is not my first class using VHDL. I had another where it was
essentially sink or swim. I did okay, but that was a while ago. Even
then, they didn't teach VHDL but rather expected you to just pick it up.

 

[springer54]

Thanks, Neo!

It looks great, but there were a few changes I needed to make to make
it a little more compatible with what I need to do. For one, I need
two separate tag boxes, etc.

So I've changed it to the following, but would like it proofread if you
(or someone else) doesn't mind:

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
LIBRARY MP2_2;
USE MP2_2.LC3b_types.all;

ENTITY tag_array IS
PORT(
TagIn : IN LC3b_tag;
WhichSet : IN std_logic_vector (2 DOWNTO 0);
WriteTag : IN std_logic;
clk : IN std_logic;
TagOut : OUT LC3b_tag
);

-- Declarations

END tag_array ;

-- hds interface_end
ARCHITECTURE untitled OF tag_array IS
type tag_array is array (0 to 7) of LC3b_tag;
signal tag : tag_array;
BEGIN
--reading
TagOut <= tag(to_integer(WhichSet(2 downto 0))) when (WriteTag = '0')
else (others => 'X');

--writing
process(clk)
begin
if(clk'event and clk= '1') then
if(WriteTag = '1') then
tag(to_integer(WhichSet(2 downto 0))) <= TagIn;
end if;
end if;
end process;
END untitled;

LC3b_tag is just a std_logic_vector(8 downto 0)

 

[springer54]

Also, I tried to reduce this for an array of 8 bits that I also need,
but the VHDL compiler spits back, "Error, aggregate cannot be of scalar
type 'std_logic'. Must be array or record"

here's the offending code (offending line marked with ***):

ENTITY eight_tall_1bit_array IS
PORT(
BitIn : IN std_logic;
WhichSet : IN std_logic_vector (2 DOWNTO 0);
WriteBit : IN std_logic;
clk : IN std_logic;
BitOut : OUT std_logic
);

-- Declarations

END eight_tall_1bit_array ;

-- hds interface_end
ARCHITECTURE untitled OF eight_tall_1bit_array IS
type bit_array is array (0 to 7) of std_logic;
signal abit : bit_array;
BEGIN
--reading
***BitOut <= abit(to_integer(WhichSet(2 downto 0))) when (WriteBit =
'0') else (others => 'X');

--writing
process(clk)
begin
if(clk'event and clk = '1') then
if(WriteBit = '1') then
abit(to_integer(WhichSet(2 downto 0))) <= BitIn;
end if;
end if;
end process;
END untitled;

 

[Neo]

The error is because you have "others" clause in else part for a signle
bit . it should just be "x".
But I dont understand why you are resorting to 'X' when its not
synthesizable.

 

[springer54]

It's the way they want it done. *shrugs*