VHDL to schematic conversion

Discussion in 'VHDL' started by khansa, Apr 6, 2005.

  1. khansa

    khansa Guest

    Please mention a tool that can accepts VHDL code and converts it into
    a circuit schematic(preferably at the register transfer level or gate
    level). Does ORCAD have such an option?
     
    khansa, Apr 6, 2005
    #1
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  2. Any decent VHDL synthesis tool (Design Compiler from Synopsys,
    Leonardo Spectrum or Precision Synthesis from Mentor,
    Synplify from Synplicity, etc etc) will do this. Don't expect
    it to be free though.

    Altera Quartus and Xilinx XST are synthesis tools from the
    device vendors that can be obtained free, at least in some
    configurations. I'm not sure whether they offer schematic
    viewers in the free versions, but they can definitely
    create netlist outputs.
    --
    Jonathan Bromley, Consultant

    DOULOS - Developing Design Know-how
    VHDL, Verilog, SystemC, Perl, Tcl/Tk, Verification, Project Services

    Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, BH24 1AW, UK
    Tel: +44 (0)1425 471223 mail:
    Fax: +44 (0)1425 471573 Web: http://www.doulos.com

    The contents of this message may contain personal views which
    are not the views of Doulos Ltd., unless specifically stated.
     
    Jonathan Bromley, Apr 6, 2005
    #2
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  3. khansa

    Hans Guest

    Hi Khansa,

    Mentor Graphics HDL designer has a code-to-graphics option (good for looking
    at the hierarchy), for gate level most synthesis tools
    (Synplify/Precision/Spectrum) have a RTL/Gatelevel schematic viewer. I am
    not sure about Orcad though,

    Hans.
    www.ht-lab.com

    | Please mention a tool that can accepts VHDL code and converts it into
    | a circuit schematic(preferably at the register transfer level or gate
    | level). Does ORCAD have such an option?
     
    Hans, Apr 6, 2005
    #3
  4. khansa

    Hendra Guest

    Xilinx ISE Webpack, which can be downloaded from Xilinx website, offer
    such an option. It's called Schematic Viewer. It's not as good as the
    40K dollars Synopsis or Synplicity tool, but it's free.

    Hendra
     
    Hendra, Apr 6, 2005
    #4
  5. khansa

    Robert Guest

    I assume what you are looking for is a tool that will take RTL and
    create a schematic at the RTL level, or at the gate level with a
    netlist, without a synthesis step. If you synthesize it, it will look
    totally different then a RTL schematic of the same circuit. You can use
    the Undertow Suite source code debugging set of software to do this.
    This software is also a fraction of the cost of a synthesis tool, and
    is very easy to use. The Undertow Suite will display a schematic of
    Verilog, VHDL, mixed Verilog and VHDL and SystemVerilog. You can
    download this software from www.veritools.com, and get a no cost
    license at .

    Robert Schopmeyer/Veritools, Inc.
     
    Robert, Apr 7, 2005
    #5
  6. Aldec's Active-HDL has a Code2Graphics converter that works quite well
    with VHDL and Verilog. It generates either block diagrams for structure
    and finite state machine bubble diagrams for certain code templates.
    It can convert to a block diagram virtually anything since it allows for
    behavioral (concurrent assignments and processes) blocks in the document...

    EG
     
    Engineering Guy, Apr 13, 2005
    #6
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