Vhdl - Xc95108 CPLD

[A2K]

Hi,

Im programming for the XC95108 CPLD and am running into a bit of a
stumbling block having never really used VHDL that much before.
Im designing a device that will act as a WAN link simulator linking two
routers by providing variable delay and speed to the network. Basically Im
using the CPLD to act as a delay buffer and a counter that divides a clock
input by 2, 4, 6, 8, 10. Now here is where Im looking for a bit of advice,
I want to generate a 2MHz square wave to act as my clock source for the
entire circuit. Now I was looking to generate the clock source (2MHz) from
the CPLD itself by writing VHDL code to do so and then use this clk signal
to clk the entire circuit. So I will be feeding the clk signal back into
the CPLD at two points, one so the signal can be divided and hence slow
the speed up and the other point to keep the delay buffer runnning. I want
to try and stay away from using a separate circuit to provide the clocking
(ie, not using the CPLD) as I ran into severe complications in doing that.


I have the code for the delay buffer written and also am getting on well
with the counter I just need to figure out a way to clock them both while
being able to change the clk frequency at one point but keeping the data
passing through.

I hope this makes sense and any advice, especially in generating the 2MHz
square wave in (VHDL) would be greatly appreciated.

Thanks in advance,

AK

 

[charles.elias]

Hi,

Im programming for the XC95108 CPLD and am running into a bit of a
stumbling block having never really used VHDL that much before.
Im designing a device that will act as a WAN link simulator linking two
routers by providing variable delay and speed to the network. Basically Im
using the CPLD to act as a delay buffer and a counter that divides a clock
input by 2, 4, 6, 8, 10. Now here is where Im looking for a bit of advice,
I want to generate a 2MHz square wave to act as my clock source for the
entire circuit. Now I was looking to generate the clock source (2MHz) from
the CPLD itself by writing VHDL code to do so and then use this clk signal
to clk the entire circuit. So I will be feeding the clk signal back into
the CPLD at two points, one so the signal can be divided and hence slow
the speed up and the other point to keep the delay buffer runnning. I want
to try and stay away from using a separate circuit to provide the clocking
(ie, not using the CPLD) as I ran into severe complications in doing that.


I have the code for the delay buffer written and also am getting on well
with the counter I just need to figure out a way to clock them both while
being able to change the clk frequency at one point but keeping the data
passing through.

I hope this makes sense and any advice, especially in generating the 2MHz
square wave in (VHDL) would be greatly appreciated.

Thanks in advance,

AK

If I understand you correctly you want to generate a 2 MHz clock using
the CPLD itself. I strongly advise against attempting this. I suggest
using a crystal oscillator for your master clock. Inexpensive versions
of these are available that will give you a symmetrical square wave
output compatible with your CPLD. This will give you an accurate,
reliable master clock.

Best regards,

Charles

 

[A2K]

Hi Charles,

Thanks for getting back to me.

Yes I agree, using a basic crystal Oscillator was indeed my original plan,
however I was just seeing if anyone had a better option ie: does the CPLD
have an in built oscillator.

But I will use a separate clock circuit using a crystal oscillator to
generate my 2MHz square wave.

One more thing Charles, do you have any tips or even VHDL code itself for
designing a divide by 2 counter??...... I want to divide my 2MHz frequency
by 2, 4, 6, & 8.

Thanks for getting back to me so quickley anyway!!

Kind regards,

Alex

 

[A2K]

Hi Charles,

Thanks for getting back to me.

Yes I agree, using a basic crystal Oscillator was indeed my original plan,
however I was just seeing if anyone had a better option ie: does the CPLD
have an in built oscillator.

But I will use a separate clock circuit using a crystal oscillator to
generate my 2MHz square wave.

One more thing Charles, do you have any tips or even VHDL code itself for
designing a divide by 2 counter??...... I want to divide my 2MHz frequency
by 2, 4, 6, & 8.

Thanks for getting back to me so quickley anyway!!

Kind regards,

Alex

 

[Peter Wallace]

The XC95 series CPLDs have no built in oscillator.

It is possible with some trickery to instantiate a ring oascillator, and
divide the output down to _approximately_ 2 MHz but this will be quite
inaccurate and unstable. Ive done this when I just needed a clock for a
state machine.

If you need an accurate 2 MHz - do what the others recommend - use a Xtal
OSC...


Peter Wallace

 

[Takuon Soho]

If I understand you correctly you want to generate a 2 MHz clock using
the CPLD itself. I strongly advise against attempting this. I suggest
using a crystal oscillator for your master clock. Inexpensive versions
of these are available that will give you a symmetrical square wave
output compatible with your CPLD. This will give you an accurate,
reliable master clock.

Best regards,

Charles

Caution, following comments are from a VHDL newbie:
Counterexamples welcome.

What???? Why not??. VHDL code to generate square
waves are well known for CPLD's. While a xtal oscillator is
fine, why in the world not use a CPLD if no xtal is avaialble?


clock <= (not clock);
wait for 5 usec;

Thanks
Tak

 

[Tim Hubberstey]

VHDL code to generate square
waves are well known for CPLD's. While a xtal oscillator is
fine, why in the world not use a CPLD if no xtal is avaialble?

Generating a clock requires some type of physical timing element. The
only such elements available that are completely within a CPLD are gate
and routing delays. Gate delays will typically vary over a 3:1 range
with temperature/supply voltage/process, assuming the vendor doesn't
tweak or shrink their process or ship you faster parts than you ordered.
This makes the variation more like 5 or 6:1. For a typical 5 ns CPLD,
using a single macrocell would give you a clock of somewhere between 100
and 600 MHz with horrible power consumption.

clock <= (not clock);
wait for 5 usec;

You're confusing what's available in *simulation* with what's available
in a real device. Even if you consumed all the logic in a modern CPLD to
generate a delay chain, you probably could do no better than 2 us total
delay.

 

[Takuon Soho]

Ah hah!

Many thanks for the info.

Tak

Generating a clock requires some type of physical timing element. The only
such elements available that are completely within a CPLD are gate and
routing delays. Gate delays will typically vary over a 3:1 range with
temperature/supply voltage/process, assuming the vendor doesn't tweak or
shrink their process or ship you faster parts than you ordered. This makes
the variation more like 5 or 6:1. For a typical 5 ns CPLD, using a single
macrocell would give you a clock of somewhere between 100 and 600 MHz with
horrible power consumption.


You're confusing what's available in *simulation* with what's available in
a real device. Even if you consumed all the logic in a modern CPLD to
generate a delay chain, you probably could do no better than 2 us total
delay.

 

[A2K]

Thanks to all!...