VHDL

  • Thread starter =?ISO-8859-1?Q?Stein_Kj=F8lstad?=
  • Start date
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=?ISO-8859-1?Q?Stein_Kj=F8lstad?=

Does there exists a software tool that parses a VHDL design project
and generates a graphical view of the entity hierarchy? For
documentation purposes. It should preferably be presented in a tree
structure.

Thanks,

Stein Kjolstad
 
T

Tim Hubberstey

Stein said:
Does there exists a software tool that parses a VHDL design project
and generates a graphical view of the entity hierarchy? For
documentation purposes. It should preferably be presented in a tree
structure.

ChipVault, http://chipvault.sourceforge.net/ , will do it although you
might find the interface is a bit "klunky".
 
A

Amontec Team

Stein said:
Does there exists a software tool that parses a VHDL design project
and generates a graphical view of the entity hierarchy? For
documentation purposes. It should preferably be presented in a tree
structure.

Thanks,

Stein Kjolstad

HDS designer will do this work greatly (The result is a little bit
depending on how is written the VHDL). Works well!

If you want to see a result, let me know. If you send me your VHDL, I
can do a graphical view of you VHDL in the minute.

And the result can be edited in your favorite HTML browser!

Larry
www.amontec.com
 

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