Warning: FlipFlops/Latches "/"ADR_reg<0>"/Q_reg" are set/reset by "". (FPGA-GSRMAP-14)

Discussion in 'VHDL' started by Martin Bammer, Nov 17, 2003.

  1. I'm working with Xilinx Foundation 2.1i and have to write a VHDL-Design
    for a Spartan XCS30. I have some curious problems that I can't get rid of.

    1)What means this line???????:
    Warning: FlipFlops/Latches "/"ADR_reg<0>"/Q_reg" are set/reset by "".

    I get warnings like the above for every signal I reset asynchronously.

    2)When I use the STARTUP-component and reset the bus ADR with this signal
    the warning disappears, BUT then the implementation process "optimizes"
    nearly all my design away!!
    Martin Bammer, Nov 17, 2003
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