What does + synthesize to?

[Kload]

Hi all,

Lets assume I'm using a Xilinx Virtex device and I have a VHDL design
that includes the following

a<=b+c;

Will the design tools (I happen to be using Foundation 2.1i) infer a
"simple" adder or will the tools automatically infer an adder that uses
the dedicated carry look ahead logic?? Will that logic be placed
appropriately (i.e. like the ACC and ADD standard components that use
the RLOC constraint)?

Thanks for your help.

 

[Ralf Hildebrandt]

Hi Kload!

Lets assume I'm using a Xilinx Virtex device and I have a VHDL design
that includes the following

a<=b+c;

Will the design tools (I happen to be using Foundation 2.1i) infer a
"simple" adder or will the tools automatically infer an adder that uses
the dedicated carry look ahead logic??

With no synthesis costraints: carry-ribble-adder, because it's the smallest.

With speed-constraints: Depending on the synthesis tool and target
library. Often Carry-Lookahead.

With something like "synthesis pragmas" (supported by Synopsys) you can
manually choose the type of adder.



Ralf