Hai friendz,
Can any one explain me the flow of this simple vhdl code.
Archit......................................
Signal TempData :Integer;
Begin
Process (b)
Begin
TempData <= 0;
If (b='1') Then
TempCount <=TempCount+1;
End If;
Dout <= TempData;
End Process;
End Arch......
may I know when the process comes to an end. (Is it only when b changes)
Can any one explain me the flow of this simple vhdl code.
Archit......................................
Signal TempData :Integer;
Begin
Process (b)
Begin
TempData <= 0;
If (b='1') Then
TempCount <=TempCount+1;
End If;
Dout <= TempData;
End Process;
End Arch......
may I know when the process comes to an end. (Is it only when b changes)