"when" assignments in process ?

S

Sylvain Munaut

Hi,


When outside of a process, to test something I can write

is_equal <= '1' when foo = bar else '0';

but how to do the same in a process ?

for now i must write

if foo=bar then
is_equal <= '1';
else
is_equal <= '0';
end if;


Which is a _lot_ longer ...

It can be shortened with

is_equal <= '0';
if foo=bar then
is_equal <= '1';
end if;

But it's still a lot longer ...



Sylvain
 
B

Ben Jones

Sylvain Munaut said:
When outside of a process, to test something I can write
is_equal <= '1' when foo = bar else '0';
but how to do the same in a process ?

-- In your package of useful functions:

function btsl(x : boolean) return std_logic is
-- btsl == Boolean To Standard Logic
begin if x then return '1'; else return '0'; end if;
end btsl;


-- In your design code:

process(...)
begin

is_equal <= btsl(foo=bar);

end process;

That is fairly short...

-Ben-
 
S

Sylvain Munaut

Indeed thanks !

I don't yet have the "function" reflex in VHDL for that kind of things.


Sylvain
 
J

Jim Lewis

Sylvain,
This is due to be fixed in the next revision of
VHDL. This revision will first be standardized by
Accellera (the group working on the revisions) in
July of 2006.

Please let your vendor know that you want them to
implement this.

Best Regards,
Jim

Hi,


When outside of a process, to test something I can write

is_equal <= '1' when foo = bar else '0';

but how to do the same in a process ?

for now i must write

if foo=bar then
is_equal <= '1';
else
is_equal <= '0';
end if;


Which is a _lot_ longer ...

It can be shortened with

is_equal <= '0';
if foo=bar then
is_equal <= '1';
end if;

But it's still a lot longer ...



Sylvain


--
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Jim Lewis
Director of Training mailto:[email protected]
SynthWorks Design Inc. http://www.SynthWorks.com
1-503-590-4787

Expert VHDL Training for Hardware Design and Verification
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
J

Jim Lewis

Ben,
This too is due to be fixed in the next revision of
VHDL. This revision will first be standardized by
Accellera (the group working on the revisions) in
July of 2006.

is_equal <= foo ?= bar ;

in addition:

Reg1Sel <= BlkSel and (Addr ?= REG1_ADDR_LOC) ;

Please let your vendor know that you want them to
implement this.

Cheers,
Jim
-- In your package of useful functions:

function btsl(x : boolean) return std_logic is
-- btsl == Boolean To Standard Logic
begin if x then return '1'; else return '0'; end if;
end btsl;


-- In your design code:

process(...)
begin

is_equal <= btsl(foo=bar);

end process;

That is fairly short...

-Ben-


--
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Jim Lewis
Director of Training mailto:[email protected]
SynthWorks Design Inc. http://www.SynthWorks.com
1-503-590-4787

Expert VHDL Training for Hardware Design and Verification
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
W

Weng Tianxiang

Hi Jim,
I miss you a lot.

How about the "orif" keyword problem? It has been 5 years since the
problem was raised and you recommented.

Weng
 

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