Why do VHDL gate level models simulate slower than verilog

Discussion in 'VHDL' started by abilash, May 17, 2005.

  1. abilash

    abilash Guest

    Hi Group,
    I am relatively new to VHDL and am tring to understand why
    VHDL gate level descriptions simulate slower than verilog models.I was
    told that it was because how the VHDL model gets evaluated (delay
    models) that makes it slower.I didnt quite follow this and if somebody
    in the group could point me towards a more detailed explanation ,it
    would be great.I would also like to know why do we see better VHDL
    performace at behavioural descriptions(as compared to verilog
    behavioural descriptions.).I am sorry if this has been discussed

    abilash, May 17, 2005
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  2. abilash

    Jim Lewis Guest

    Seeing simlar observations to yours, for the VHDL-200X effort
    I proposed that VHDL accept Verilog gate level description as
    a valid VHDL format. The response I received from at least
    one EDA vendor was that VHDL gate level descriptions could
    be as fast as Verilog gate level descriptions if the vendors
    spent more time optimizing them.

    If you want VHDL gate level designs to be faster, it is a
    matter of making sure your vendors know that they need to
    spend the time making them faster.

    Best Regards,
    Jim Lewis

    Jim Lewis
    Director of Training mailto:
    SynthWorks Design Inc. http://www.SynthWorks.com

    Expert VHDL Training for Hardware Design and Verification
    Jim Lewis, May 17, 2005
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