Xilinx ISE Webpack problem

Discussion in 'VHDL' started by u_stadler, Feb 12, 2006.

  1. u_stadler

    u_stadler Guest


    i donwloaded the new ise 8.1 version (i was working with 7.1 before)
    and started a new project. wen i generated a new source file i get the
    message :

    ProjectMgmt - "D:/FPGA/Clock_32_MHz.ngr" line 0 duplicate design unit:

    Does anyone know what that means?

    u_stadler, Feb 12, 2006
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  2. u_stadler

    Zara Guest

    Just ignore it. I have been ingoring suche messages for 1 month, with
    no problems at all. I suppose it is one of this messages that come out
    of having little time to test new versions, and will be corrceted on
    future SP


    Zara, Feb 13, 2006
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