Xilinx Webpack

Discussion in 'VHDL' started by mep, Sep 26, 2004.

  1. mep

    mep Guest

    Hi there
    I teach classes in VHDL and uses Xilinx Webpack as a tool for this.
    Unfortunately, the new module wizard always set type std_logic for
    I/O-lines. This makes it very hard to learn the students about the other
    types.
    Does anybody know if this can be changed - and how?
    Mogens
     
    mep, Sep 26, 2004
    #1
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  2. Consider using the Modelsim program included
    with webpack to teach VHDL language.

    -- Mike Treseler
     
    Mike Treseler, Sep 27, 2004
    #2
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  3. mep

    mep Guest

    Hi Mike
    Not really, because in all the drills, the students end up programming a
    CPLD or a FPGA from Xilinx. In this way they can themselves check the
    solutions.
    But maybe I should take a closer look, because there are a number of
    problems with webpack.
    Mogens
     
    mep, Sep 27, 2004
    #3
  4. mep

    Alex Gibson Guest

    Easy to copy the code from in modelsimand paste it back into project
    navigator.
    Or use the add a copy of the source feature in
    the module wizard and in project navigator.

    We use the full version of ise in the lab
    (via university program http://university.xilinx.com/ )
    and students have webpack to use at home.

    If you have problems with webpack go here
    http://xup.msu.edu/support/index.htm

    Surely it is up to the instructor to
    teach them about all the types in vhdl not the module wizard ?

    Could always set a few small assignments where they have to use
    some of the other types or give them a limit on the number
    of std_logic I/Os they can use.


    Alex
     
    Alex Gibson, Sep 28, 2004
    #4
  5. skip any wizard !
    Your students need to learn the basic of VHDL and NOT the software troubles.

    You can provide some VHDL generic code of DFF, shift register, counter ...

    For a nice VHDL memo goto http://www.amontec.com/fix/vhdl_memo/index.html

    Larry
     
    Laurent Gauch, Sep 28, 2004
    #5
  6. mep

    rickman Guest

    I don't see a default type in a wizard as "troubles". Sure the GUI
    stuff will have more bugs than simpler software, but the GUI is what
    most people use and it is not unreasonable to use it in a classroom. I
    especially like the idea of not making students spend time typing in
    lists of signals several times for module definitions. I prefer that
    they learn the basics of how to use an HDL and how to code. I almost
    never start from scratch in my VHDL. I copy from an old module and just
    change the names. I even have defined editor macros to allow me to type
    in the signal names once and do a search and replace to change the list
    to the other formats, component declarations and instantiations.

    Why make the students do a lot of work they won't be doing in the real
    world? I hated that sort of make-work when I was in school.

    --

    Rick "rickman" Collins


    Ignore the reply address. To email me use the above address with the XY
    removed.

    Arius - A Signal Processing Solutions Company
    Specializing in DSP and FPGA design URL http://www.arius.com
    4 King Ave 301-682-7772 Voice
    Frederick, MD 21701-3110 301-682-7666 FAX
     
    rickman, Sep 29, 2004
    #6
  7. The trouble is non-portable code and vendor-specific libraries.
    I agree that the students should have an editor that can
    copy ports and paste signal lists, instances and testbench templates.
    The point is that they ought to be learning how to
    infer registers, counters, shifters and RAMs from portable VHDL code,
    not wiring up magic boxes.

    By learning simulation first, the students can eliminate
    errors and verify the module's function before attempting
    synthesis. In a simulation environment, you can jump
    to syntax errors and trace code for debugging.

    -- Mike Treseler
     
    Mike Treseler, Sep 29, 2004
    #7
  8. In my experience, if you use anything other than Std_Logic(_Vector) for IOs
    from a device your Vital simulation wont work; plain fact. Therefore Xilinx
    are simply following "best" practice.

    Equally, I would take a lot of persuasion that any types beyond
    Std_Logic(_Vector), Std_ULogic (for resolved signal implementations),
    Unsigned, Signed, enumerated types, and perhaps a few "specials" have a
    serious role in synthesis.

    Martin
     
    Martin Bishop, Sep 29, 2004
    #8
  9. mep

    mpe Guest

    Hi Mike,

    <not wiring up magic boxes>. magic or black! You hit the nail on the head..
    I know persons, that argues that it is not nessary to learn types ( and
    sensitivity list and a lot more that I fell basic). Give the students 10-15
    templates and scematic in webpack and you have a beginners course!

    Maybe we should start a group discussing the pensum for a XX-lessons
    beginners course. And courses to follow!

    I feel simulation - even (or especially) on a beginners course - is very
    important. It teaches the students a lot, but mostly being systematic, set
    goals and reach them!

    mogens
     
    mpe, Sep 29, 2004
    #9
  10. Yes I'm OK with you.
    But it is still depending on the student level and where is the VHDL
    'Real World'.

    VHDL 'real world' may be :
    - VHDL RTL design
    - VHDL System design
    - (testbench)

    RTL design is bottom-up concept
    System design is top-down concept

    So, the 'Real world'(industrial project) is somewhere between
    'bottom-up' and 'top-down' concept.

    Now, with students, is this better to start with RTL Design or System
    design?

    For me, it is still better to start with RTL design -> for better
    Hardware understandings.

    Larry
    www.amontec.com
     
    Laurent Gauch, Sep 30, 2004
    #10
  11. mep

    rickman Guest

    What code is non-portable just because it is generated by a wizard? I
    am not familiar with this wizard, but genrating a boiler plate module
    from a list of IOs does not sound very problimatic to me.

    You are talking about something different I believe. That would be
    instantiated modules and FSM generators. Very different from what was
    being discussed.

    Yes, but they need to be *taught* about synthesis and I always recommend
    that they design the logic structure before they start *any* coding or
    simulation.

    --

    Rick "rickman" Collins


    Ignore the reply address. To email me use the above address with the XY
    removed.

    Arius - A Signal Processing Solutions Company
    Specializing in DSP and FPGA design URL http://www.arius.com
    4 King Ave 301-682-7772 Voice
    Frederick, MD 21701-3110 301-682-7666 FAX
     
    rickman, Sep 30, 2004
    #11
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