Xilinx XST Error

[Alex McHale]

At the bottom of this post is the code.

First, let me say that I have run this "program" through a TBW, and it
seems to simulate correctly.

Second, I'll describe what this module does (or at least, should do).
8 bytes (along with 5 address bits that are carried). When 8 bytes
come in, it outputs all 8 at once in a 64 bit value (again, along with
the carried 5 bit address).

The latch line is mostly simply passed through, except that it is
additionally used to reset the buffer pointer.

Am I making this task overly complex? If not, what's going on with it?

When I run the "implement design" task, I get the following warnings /
errors:



=========================================================================
* HDL Analysis
*
=========================================================================
Analyzing Entity <queue> (Architecture <behavioral>).
WARNING:Xst:790 - "C:/xilinx/tutorial/queue.vhd" line 46: Index
value(s) does not match array range, simulation mismatch.
INFO:Xst:1433 - Contents of array <data_buffer> may be accessed with an
index that exceeds the array size. This could cause simulation
mismatch.
ERROR:Xst:827 - "C:/xilinx/tutorial/queue.vhd" line 23: Signal
DATA_OUT<57> cannot be synthesized, bad synchronous description.




I'm indeed new to VHDL, and I'm just not clear on what the problem is
here. Any help would be greatly, greatly appreciated. I can supply a
zip of the project to anyone interested in helping enough for that.

Thanks!

Alex McHale








library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity queue is
Port ( DATA_IN : in STD_LOGIC_VECTOR (7 downto 0);
LATCH_IN : in STD_LOGIC;
CLOCK_IN : in STD_LOGIC;
ADDRESS_IN : in STD_LOGIC_VECTOR (4 downto 0);
DATA_OUT : out STD_LOGIC_VECTOR (63 downto 0);
LATCH_OUT : out STD_LOGIC;
CLOCK_OUT : out STD_LOGIC;
ADDRESS_OUT : out STD_LOGIC_VECTOR (4 downto 0));
end queue;

architecture Behavioral of queue is
type ram_type is array (0 to 7) of STD_LOGIC_VECTOR (7 downto 0);
signal data_buffer : ram_type := ("00000000", "00000000", "00000000",
"00000000", "00000000", "00000000", "00000000", "00000000");
signal buffer_write_offset : STD_LOGIC_VECTOR (3 downto 0) := "0000";
signal address_buffer : STD_LOGIC_VECTOR (4 downto 0) := "00000";
begin
process (CLOCK_IN, LATCH_IN)
begin
if rising_edge( LATCH_IN ) then
buffer_write_offset <= "0000";
LATCH_OUT <= '1';
elsif falling_edge( LATCH_IN ) then
LATCH_OUT <= '0';
elsif rising_edge( CLOCK_IN ) then
CLOCK_OUT <= '0';

if buffer_write_offset = "0000" then
DATA_OUT( 7 downto 0 ) <= data_buffer( 0 );
DATA_OUT( 15 downto 8 ) <= data_buffer( 1 );
DATA_OUT( 23 downto 16 ) <= data_buffer( 2 );
DATA_OUT( 31 downto 24 ) <= data_buffer( 3 );
DATA_OUT( 39 downto 32 ) <= data_buffer( 4 );
DATA_OUT( 47 downto 40 ) <= data_buffer( 5 );
DATA_OUT( 55 downto 48 ) <= data_buffer( 6 );
DATA_OUT( 63 downto 56 ) <= data_buffer( 7 );
ADDRESS_OUT <= address_buffer;
CLOCK_OUT <= '1' after 1ns;
end if;

data_buffer( conv_integer( buffer_write_offset ) ) <= DATA_IN after
5ns;
address_buffer <= ADDRESS_IN after 5ns;
buffer_write_offset <= (buffer_write_offset + 1) and "0111" after
10ns;
end if;
end process;
end Behavioral;

 

[Rtafas]

Hello,

You have 8 elements on data buffer. 3 bits to address it, from 0 to 7.
buffer_write_offset is 4 bits wide. it addresses 0 to 15. Correct the
size of bufferwrite_offset or increase the ram size.

About the error: it won´t compile with all these edges, with "after"
and "wait" statments. Search for synthesizable VHDL references. this is
a simulation model only.

Best regards,

RTafas



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