2002 buffer mode port support?

[Evan Lavelle]

Any idea how widely the buffer mode fix is supported now? I've only
tried on ModelSim, which is Ok with it.

Thanks -

Evan

 

[Mike Treseler]

Any idea how widely the buffer mode fix is supported now? I've only
tried on ModelSim, which is Ok with it.

Haven't tried.
Quartus 9.0 analysis settings are 87 or 93,
but I expect some 2002 might be tolerated.
If you send me a code sample, I will run it for you.


-- Mike Treseler

 

[Evan Lavelle]

If you send me a code sample, I will run it for you.

Thanks. Here's the example from the FAQ (4.2.33):

entity SRLatch is
port( S, R: in bit;
Q, QBar: buffer bit); -- "Q" and "Qbar" are of
-- mode buffer!
end SRLatch;

architecture Structure of SRLatch is
component Nor2
port( I1, I2: in bit;
O: out bit); -- "O" is of mode out
end component;
begin
Q1: Nor2 port map (I1 => S, -- ok
I2 => QBar, -- ok
O => Q); -- illegal

Q2: Nor2 port map (I1 => R, -- ok
I2 => Q, -- ok
O => QBar); -- illegal
end Structure;

If it compiles without reporting errors (the 'illegal' lines), then
you've got the 2002 fix.

-Evan

 

[Mike Treseler]

If it compiles without reporting errors (the 'illegal' lines), then
you've got the 2002 fix.

Seems nor2 is reserved by Quartus, but other than that.
All is well. RTL schematic is as expected.

-- Mike


_____________________________________________________________________
entity Nor_2 is
port(I1, I2 : in bit;
O : out bit); -- "O" is of mode out
end;

architecture Synth of Nor_2 is
begin
O <= not(I1 or I2);
end;
----------------------------------------------------------------------
entity SRLatch is
port(S, R : in bit;
Q, QBar : buffer bit); -- "Q" and "Qbar" are of mode buffer!
end SRLatch;

architecture Structure of SRLatch is
begin
Q1 : work.Nor_2 port map (I1 => S, -- ok
I2 => QBar, -- ok
O => Q); -- illegal

Q2 : work.Nor_2 port map (I1 => R, -- ok
I2 => Q, -- ok
O => QBar); -- illegal
end Structure;


--Info : *******************************************************************
--Info : Running Quartus II Analysis & Synthesis
--Info : Version 9.0 Build 184 04/29/2009 Service Pack 1 SJ Full Version
--Info : Processing started : Thu Nov 19 15 : 03 : 59 2009
--Info : Command : quartus_map --read_settings_files=on
--write_settings_files=off vhdl02buffer -c vhdl02buffer
--Info : Found 4 design units, including 2 entities, in source file
.../vhdl02buffer.vhd
--Info : Found design unit 1 : Nor_2-Synth
--Info : Found design unit 2 : SRLatch-Structure
--Info : Found entity 1 : Nor_2
--Info : Found entity 2 : SRLatch
--Info : Elaborating entity "SRLatch" for the top level hierarchy
--Info : Elaborating entity "Nor_2" for hierarchy "Nor_2:Q1"
--Info : Implemented 6 device resources after synthesis - the final
resource count might be different
--Info : Implemented 2 input pins
--Info : Implemented 2 output pins
--Info : Implemented 2 logic cells
--Info : Quartus II Analysis & Synthesis was successful. 0 errors, 0
warnings
--Info : Peak virtual memory : 194 megabytes
--Info : Processing ended : Thu Nov 19 15 : 04 : 15 2009
--Info : Elapsed time : 00 : 00 : 16
--Info : Total CPU time (on all processors) : 00 : 00 : 03
--Info : *******************************************************************
--Info : Running Quartus II Netlist Viewers Preprocess
--Info : Version 9.0 Build 184 04/29/2009 Service Pack 1 SJ Full Version
--Info : Processing started : Thu Nov 19 15 : 04 : 47 2009
--Info : Command : quartus_rpp vhdl02buffer -c vhdl02buffer
--netlist_type=sgate
--Info : Quartus II Netlist Viewers Preprocess was successful. 0 errors,
0 warnings
--Info : Peak virtual memory : 118 megabytes
--Info : Processing ended : Thu Nov 19 15 : 04 : 49 2009
--Info : Elapsed time : 00 : 00 : 02
--Info : Total CPU time (on all processors) : 00 : 00 : 00

 

[JimLewis]

Perhaps we should also check and see how the support for VHDL-2008
reading an out port.

Cheers,
Jim