7 segment 0-99 converter

[xenakis]

Hi, I'm trying to make a decimal to 7 segment display converter for numbers from 0 to 99 in dataflow with synchronous clock (using a Clock process). It's my first VHDL attempt so I have some problems. My thought was to make an assignemt like this:

S(0) <= (P(0)) OR (P(2)) OR (NOT P(1) AND NOT P(3)) OR (P(1) AND P(3));
S(1) <= (NOT P(1)) OR (P(2) AND P(3)) OR (NOT P(2) AND NOT P(3));
S(2) <= (P(1) OR NOT P(2) OR P(3));
S(3) <= (P(0)) OR (NOT P(1) AND P(2)) OR (P(2) AND NOT P(3)) OR (NOT P(1) AND NOT P(2) AND NOT P(3)) OR (P(1) AND NOT P(2) AND P(3));
S(4) <= (P(2) AND NOT P(3)) OR (NOT P(0) AND NOT P(1) AND NOT P(3)) OR (P(0) AND NOT P(3));
S(5) <= (P(0)) OR (NOT P(2) AND NOT P(3)) OR (P(1) AND NOT P(2)) OR (P(1) AND NOT P(3));
S(6) <= (P(0)) OR (P(2) AND NOT P(3)) OR (P(1) AND NOT P(2)) OR (NOT P(0) AND NOT P(1) AND P(2));

where

P : in  BIT_VECTOR(0 TO 3);
S : out  BIT_VECTOR(0 TO 6));

but this is only for one 7 segment display, I need two of them and I don't know how to manage it. Moreover, how do I treat the clock process?
I'll appreciate any kind of suggestion.
Thank you.

 

[joris]

Unless I'm totally misunderstanding the code you have there is to translate
a binary number (0000 - 1001) into the different segments.

I'll assume you'll give it the name bin2seg

You will also need a 'counter' entity which, given a clock input, will increment such that:

inc state  next | C
0   no change    0
1   0000  0001   0
1   0001  0010   0
1   0010  0011   0
1   0011  0100   0
1   0100  0101   0
1   0101  0110   0
1   0110  0111   0
1   0111  1000   0
1   1000  1001   0
1   1001  0000   1

Assuming that's called bcd9Counter

Then you can use these entities as building parts:

bcd1map : bcd9Counter port map ( clk, b1In, '1' -- for increment
  b1Out, c1);
bcd2map : bcd9Counter port map ( clk, b2In, c1,
  b2Out, c2);

bin2seg1Map: bin2seg port map (b1In, seg1);
bin2seg2Map: bin2seg port map (b2In, seg2);