A constant with if-else-if

[Kevin Neilson]

How do I embed an if-else-if within a constant definition? This doesn't
compile in Modelsim:

constant Y : integer := A when A>B else B;

If I use the math_real library, I can do this:

constant Y : integer := integer(realmax(real(A),real(B)));

but I'd still like a general solution. Must I write a constant function?

-Kevin

 

[KJ]

How do I embed an if-else-if within a constant definition? This doesn't
compile in Modelsim:

constant Y : integer := A when A>B else B;

If I use the math_real library, I can do this:

constant Y : integer := integer(realmax(real(A),real(B)));

but I'd still like a general solution. Must I write a constant function?

Yes, you have to write a function.

Kevin Jennings

 

[Andy]

How do I embed an if-else-if within a constant definition? This doesn't
compile in Modelsim:

constant Y : integer := A when A>B else B;

If I use the math_real library, I can do this:

constant Y : integer := integer(realmax(real(A),real(B)));

but I'd still like a general solution. Must I write a constant function?

-Kevin

Yes, a function would work, as would a secondary constant array,
indexed with boolean.

Andy

 

[HT-Lab]

The good news is that the functions maximum and minimum are
language defined in the Accellera VHDL-2006 / IEEE VHDL-2008 (yet
to be balloted) for all numeric (and scalar) types.

I would recommend submitting a bug report to the tool vendor
if they have not implemented them yet. Warning, if you don't
do this, then they think you are not interested in the new
standard.

I can't agree more with Jim, look at the supported language constructs and
you will soon agree with me that we need this standard ASAP!

Come on guys speak to your favourite EDA vendor/distributor and log an
Enhancement Request (ER) to have this standard supported. I have already
done this for Modelsim but it seems I am one of the few :-(

Hans
www.ht-lab.com

 

[Kevin Neilson]

The good news is that the functions maximum and minimum are
language defined in the Accellera VHDL-2006 / IEEE VHDL-2008 (yet
to be balloted) for all numeric (and scalar) types.

I would recommend submitting a bug report to the tool vendor
if they have not implemented them yet. Warning, if you don't
do this, then they think you are not interested in the new
standard.

Best,
Jim

I don't know if I'll waste the time. I started writing to vendors after
Verilog-2001 came out and the turn of the century was long forgotten
before any of those features (like generate) got implemented. I gather
that most coders write non-parameterizable highly structural code so
maybe the vendors don't need to support these constructs.

Besides, I want SystemVerilog to emerge as the winner, so I'm trying to
sabotage all other languages.
-Kevin

 

[Mike Treseler]

Yes, a function would work, as would a secondary constant array,
indexed with boolean.

like this:
http://groups.google.com/groups/search?q=active_high+sul_bool

 

[Kevin Neilson]

like this:
http://groups.google.com/groups/search?q=active_high+sul_bool

The Verilog construct is nice in these situations:

parameter X = (A>B) ? A : B;

 

[Mike Treseler]

The Verilog construct is nice in these situations:

parameter X = (A>B) ? A : B;

I thought the situation was being forced to write vhdl

http://groups.google.com/groups/search?q=boolean+function+expr_if

 

[KJ]

The Verilog construct is nice in these situations:

   parameter X = (A>B) ? A : B;

The VHDL construct is pretty nice too.

constant X: integer := maximum(A_scalar,B_scalar);
constant X: integer := maximum(A_vector);

I takes a couple minutes to write and test all the overloaded
'maximum' and 'minimum' functions that work with two arguments of all
the basic types or arrays of all the basic types.

KJ

 

[Kevin Neilson]

I thought the situation was being forced to write vhdl

http://groups.google.com/groups/search?q=boolean+function+expr_if

I do have to use VHDL. I was just wishing I could do the Verilog thing,
with minimum verbosity.

 

[Guest]

I do have to use VHDL. I was just wishing I could do the Verilog thing,
with minimum verbosity.

Why the reluctance to write a function? I don't see how you can get
much
less verbose, or more self-evident, than
max(a,b)
and the function itself can be written just once, put in a package,
and used wherever you feel like it. "Verilog is less verbose than
VHDL"
is simply a myth.

Same deal for all the type conversions that people get so worked-up
about. If you find yourself using a particular type conversion more
than once, write a function to do it.

 

[Mike Treseler]

I do have to use VHDL. I was just wishing I could do the Verilog thing,
with minimum verbosity.

I can hide verbosity, but not eliminate it,
by packaging functions and types that
do things my way. The upside is that this
is possible. The downside is that this
is sometimes necessary.

As far as the '?' function goes,
I can't improve on Jonathan's function.
But I happen to think that the unsweetened version,

if a>b then x:=a;
else x:=b;
end if;

has the verbosity about right
and is just as easy to read as

parameter X = (A>B) ? A : B;

-- Mike Treseler

 

[KJ]

I do have to use VHDL.  I was just wishing I could do the Verilog thing,
with minimum verbosity.

Even if you think use of the 'maximum' function is not adequate
because it is a specific case of your use of Verilog's '?' it is hard
to say that VHDL is more verbose with this syntax which is equivalent
to the Verilog '?'

X := sel(A>B, A, B);

It implies that you write once (and put it in your package of commonly
used VHDL helper functions) overloaded versions of the 'sel' function
that are of the form

function sel(Cond: BOOLEAN; A,B: integer) return integer;
function sel(Cond: BOOLEAN; A,B: real) return real;
function sel(Cond: BOOLEAN; A,B: time) return time;
function sel(Cond: BOOLEAN; A,B: std_logic) return std_logic;
...etc...

Kevin Jennings