a little help for a learner

[crackle24]

i have just started learning vhdl.
dere r a few things dat dont work and i dont know why,and i was hoping
to find some help here.

firstly i tried writing a code using 'when ...else' but i get a syntax
error i dont know why.
and secondly i tried to increment a bit vector value with de statement
cout:=count + "001";
is dis right.
de same works when i declared count as std_logic.

 

[Ajeetha]

Hi,
As a learner, another important aspect to learn is "how to ask" to
get quick help. In this case, show us your piece of code to help you
better.

On second issue - which packages are you using?

Regards
Ajeetha
www.noveldv.com

 

[Ralf Hildebrandt]

i have just started learning vhdl.
dere r a few things dat dont work and i dont know why,and i was hoping
to find some help here.

firstly i tried writing a code using 'when ...else' but i get a syntax
error i dont know why.

Post your code and the error message.

and secondly i tried to increment a bit vector value with de statement

Don't use bit or bit_vector. Bit can only be '0' or '1' and there is no
'X'. Use std_ulogic(_vector) (for single-source signals) or
std_logic(_vector) (for multi-source signals, as for tri-state busses).

cout:=count + "001";
is dis right.

This strongly depends on the library you use. It is recommended to
use IEEE.numeric_std.all;

Then you have several option how to do arithmetics:
* if count is of type unsigned, write
count:=count + 1; -- addition of unsigned and integer
* if count is of type signed, write
count:=count + 1; -- addition of signed and integer
* if count is of type std_ulogic_vector, write
eighter
count:= std_ulogic_vector(unsigned(count) + 1);
or
count:= std_ulogic_vector(signed(count) + 1);

The decision between signed and unsigned is important if negative
numbers may occur and therefore this strong definition how to threat
count is necessary - even if it looks bad.

Look into IEEE.numeric_std.all to see what additions are supported.
Convert your signals to types, that can be used with these additions.

de same works when i declared count as std_logic.

-> You use probably IEEE.std_logic_arith.all; with is NOT recommended,
because this is not a standard library.


Note, that something like count:=count+1; should be only used in
synchronous processes (inside a "if rising_edge(clock)").


Ralf

 

[crackle24]

firstly than u for ur reply.
i get 2 use xilinx foundation (i think its just a sampler) at de moment
but later on i'll be using xilinx 7.1. is dis what u meant by package?
about when ...else,de code i used is:
--start of code.
architecture df of mux1 is
begin
z<=i0 when s="00" else <--shows syntax error.dats it.
z<=i1 when s="01" else
..
..
..
--end of code

well i was using IEEE.std_logic_arith.all and the count:=count +1 was
in a clocked sequential process .I used an integer value for count and
it did work.but i wonder if it's right to do so.
thanks again.

 

[Ralf Hildebrandt]

i get 2 use xilinx foundation (i think its just a sampler) at de moment
but later on i'll be using xilinx 7.1. is dis what u meant by package?

No - a package is something similar to C header files.
If you write
Library IEEE; -- you declare where to search
use IEEE.numeric_std.all; -- you select everything
-- from the package numeric_std.

about when ...else,de code i used is:
--start of code.
architecture df of mux1 is
begin
z<=i0 when s="00" else <--shows syntax error.dats it.
z<=i1 when s="01" else
..
..
..
--end of code

This is an easy syntax error, that has nothing to do with packages.

z<=i0 when s="00" else
i1 when s="01" else
...

well i was using IEEE.std_logic_arith.all

Don't do this. This is not a standard package. There are different
implementations. Every toolbox has its own. Use numeric_std!

and the count:=count +1 was
in a clocked sequential process .

Right - otherwise you would describe an infinite loop.

I used an integer value for count and
it did work.but i wonder if it's right to do so.

You can use whatever type is suitable for you. It is recommended to use
* std_ulogic - for logic
* std_logic - for logic, that may be tri-state
* unsigned / signed - if you need arithmetics _and_ vectors
* integer - if your code should look better (but be aware, that integer
is a32 bit type, while unsigned / signed can be wider)

Wheter you ca do arithmetics depends on functions provided in packages.
E.g. Numeric_std does not provide Addition for std_ulogic_vectors - for
a very good reason! Just look into the packages and there you will see,
which functions are available.

Ralf