A question about syntax of VHDL

J

Jim Huang

Can I write the if condition like this? Assume

signal A std_logic_vector(29 downto 0);

if A = (others => '0´) then
.................
end if;

if this syntax is invalid, how should I write it? any simple way.
I do not want to put 30 zeros here.

Can I write the condition as
A = "00" & 0x0000000

Thanks
Jim
 
J

Jim Huang

Hi

Thanks, but I think you misunderstood me. I asked if I can compare the
signal A with (other => '0') in the IF clause.
 
M

Mohammed A khader

HI Jim,
if A = (others => '0´) then

will give you error as

others must be use with constrained array. (others => '0') is not
enough to know the length of the array.
Can I write the condition as
A = "00" & 0x0000000

Yes you can write the numbers in hex or oct

if ( A = X"0000") then -- will work fine but make sure that type A
is a vector of bit or std_logic.

-- Mohammed A Khader.
 
M

Mohammed A khader

HI Jim,
if A = (others => '0´) then

will give you error as

others must be use with constrained array. (others => '0') is not
enough to know the length of the array.
Can I write the condition as
A = "00" & 0x0000000

Yes you can write the numbers in hex or oct

if ( A = X"0000") then -- will work fine but make sure that type A
is a vector of bit or std_logic.

-- Mohammed A Khader.
 
I

info_

Jim said:
Can I write the if condition like this? Assume

signal A std_logic_vector(29 downto 0);

if A = (others => '0´) then
.................
end if;

if this syntax is invalid, how should I write it?

One clean solution is to use subtypes and qualified expression :

subtype SLV30 is std_logic_vector(29 downto 0);

signal A : SLV30;

if A = SLV30'(others=>'0') then -- will work

As you noticed , hexadecimal notation isn't for fun except
on exact multiple of four bits...

Other solution :

if (unsigned(A)=0 then

etc...

Bert Cuzeau
 

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