"ack" is reserved keyword in VHDL?

[rl]

Consider the piece of code below, "ack" is not declared, yet it does
not give any compiler/synthesiser errors. Why is this, is "ack"
somehow reserved?

ENTITY test IS
PORT
(
output : OUT bit
);
END ENTITY;

ARCHITECTURE rtl OF test IS
BEGIN
output <= '1' WHEN (ack = '1') ELSE '0';
END rtl;

 

[HT-Lab]

Consider the piece of code below, "ack" is not declared, yet it does
not give any compiler/synthesiser errors. Why is this, is "ack"
somehow reserved?

ENTITY test IS
PORT
(
output : OUT bit
);
END ENTITY;

ARCHITECTURE rtl OF test IS
BEGIN
output <= '1' WHEN (ack = '1') ELSE '0';
END rtl;

Yes, it is defined in the STD package;

package standard is
type boolean is (false,true);
type bit is ('0', '1');
type character is (
nul, soh, stx, etx, eot, enq, ack, bel,
bs, ht, lf, vt, ff, cr, so, si,
dle, dc1, dc2, dc3, dc4, nak, syn, etb,
can, em, sub, esc, fsp, gsp, rsp, usp, ......


Hans
www.ht-lab.com

 

[kennheinrich]

Yes, it is defined in the STD package;

package standard is
type boolean is (false,true);
type bit is ('0', '1');
type character is (
nul, soh, stx, etx, eot, enq, ack, bel,
bs, ht, lf, vt, ff, cr, so, si,
dle, dc1, dc2, dc3, dc4, nak, syn, etb,
can, em, sub, esc, fsp, gsp, rsp, usp, ......

Hanswww.ht-lab.com

If you actually have ack defined in your architecture as a signal, it
should hide standard's enum definition anyway. It's not that it's a
reserved word, it's just that the definition in 'standard' happens to
be visible there. You can hide it again with a local definition and
have no problem.

- Kenn