"ack" is reserved keyword in VHDL?

Discussion in 'VHDL' started by rl, Jul 17, 2008.

  1. rl

    rl Guest

    Consider the piece of code below, "ack" is not declared, yet it does
    not give any compiler/synthesiser errors. Why is this, is "ack"
    somehow reserved?

    ENTITY test IS
    PORT
    (
    output : OUT bit
    );
    END ENTITY;

    ARCHITECTURE rtl OF test IS
    BEGIN
    output <= '1' WHEN (ack = '1') ELSE '0';
    END rtl;
    rl, Jul 17, 2008
    #1
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  2. rl

    HT-Lab Guest

    "rl" <> wrote in message
    news:...
    > Consider the piece of code below, "ack" is not declared, yet it does
    > not give any compiler/synthesiser errors. Why is this, is "ack"
    > somehow reserved?
    >
    > ENTITY test IS
    > PORT
    > (
    > output : OUT bit
    > );
    > END ENTITY;
    >
    > ARCHITECTURE rtl OF test IS
    > BEGIN
    > output <= '1' WHEN (ack = '1') ELSE '0';
    > END rtl;


    Yes, it is defined in the STD package;

    package standard is
    type boolean is (false,true);
    type bit is ('0', '1');
    type character is (
    nul, soh, stx, etx, eot, enq, ack, bel,
    bs, ht, lf, vt, ff, cr, so, si,
    dle, dc1, dc2, dc3, dc4, nak, syn, etb,
    can, em, sub, esc, fsp, gsp, rsp, usp, ......


    Hans
    www.ht-lab.com
    HT-Lab, Jul 17, 2008
    #2
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  3. rl

    Guest

    On Jul 17, 3:32 am, "HT-Lab" <> wrote:
    > "rl" <> wrote in message
    >
    > news:...
    >
    > > Consider the piece of code below, "ack" is not declared, yet it does
    > > not give any compiler/synthesiser errors. Why is this, is "ack"
    > > somehow reserved?

    >
    > > ENTITY test IS
    > > PORT
    > > (
    > > output : OUT bit
    > > );
    > > END ENTITY;

    >
    > > ARCHITECTURE rtl OF test IS
    > > BEGIN
    > > output <= '1' WHEN (ack = '1') ELSE '0';
    > > END rtl;

    >
    > Yes, it is defined in the STD package;
    >
    > package standard is
    > type boolean is (false,true);
    > type bit is ('0', '1');
    > type character is (
    > nul, soh, stx, etx, eot, enq, ack, bel,
    > bs, ht, lf, vt, ff, cr, so, si,
    > dle, dc1, dc2, dc3, dc4, nak, syn, etb,
    > can, em, sub, esc, fsp, gsp, rsp, usp, ......
    >
    > Hanswww.ht-lab.com


    If you actually have ack defined in your architecture as a signal, it
    should hide standard's enum definition anyway. It's not that it's a
    reserved word, it's just that the definition in 'standard' happens to
    be visible there. You can hide it again with a local definition and
    have no problem.

    - Kenn
    , Jul 18, 2008
    #3
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