Adding to vector

Discussion in 'VHDL' started by thecity00, Dec 6, 2009.

  1. thecity00

    thecity00

    Joined:
    Dec 6, 2009
    Messages:
    1
    Hey all,
    I am having an issue where adding 1 to a vector is resulting in the vector incrementing by 8 in decimal, while I want it to just increment by 1.

    Here is my code:

    Code:
    library ieee;
    use IEEE.STD_LOGIC_1164.ALL;
    use IEEE.STD_LOGIC_ARITH.ALL;
    use IEEE.STD_LOGIC_UNSIGNED.ALL;
    
    entity counter is
       port( 
    		CLK: in std_logic;
    		output: out std_logic_vector(0 to 3);
    end counter;
    
    architecture behavioral of counter is
       signal temp: std_logic_vector(0 to 3);
    	begin process(CLK)
    	begin
    		if(CLK'event and CLK='1') then
    			temp <= (temp + 1);
    			end if;
    	end process;
    	output <= temp;
    end behavioral;
    
    This is how the output is incrementing:
    0,8,4,12,2,10

    Seems it is adding 8...


    Thanks in advance
    thecity00, Dec 6, 2009
    #1
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  2. thecity00

    jeppe

    Joined:
    Mar 10, 2008
    Messages:
    348
    Location:
    Denmark
    Hi

    Try this and note the difference between to and downto.

    Code:
    library ieee;
    use IEEE.STD_LOGIC_1164.ALL;
    use IEEE.STD_LOGIC_ARITH.ALL;
    use IEEE.STD_LOGIC_UNSIGNED.ALL;
    
    entity counter is
       port( 
    		CLK: in std_logic;
    		output: out std_logic_vector(3 downto 0);
    end counter;
    
    architecture behavioral of counter is
       signal temp: std_logic_vector(3 downto 0);
    	begin process(CLK)
    	begin
    		if(CLK'event and CLK='1') then
    			temp <= (temp + 1);
    			end if;
    	end process;
    	output <= temp;
    end behavioral;
    jeppe, Dec 6, 2009
    #2
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