Adding to vector

[thecity00]

Hey all,
I am having an issue where adding 1 to a vector is resulting in the vector incrementing by 8 in decimal, while I want it to just increment by 1.

Here is my code:

library ieee;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity counter is
   port( 
		CLK: in std_logic;
		output: out std_logic_vector(0 to 3);
end counter;

architecture behavioral of counter is
   signal temp: std_logic_vector(0 to 3);
	begin process(CLK)
	begin
		if(CLK'event and CLK='1') then
			temp <= (temp + 1);
			end if;
	end process;
	output <= temp;
end behavioral;

This is how the output is incrementing:
0,8,4,12,2,10

Seems it is adding 8...


Thanks in advance

 

[jeppe]

Hi

Try this and note the difference between to and downto.

library ieee;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity counter is
   port( 
		CLK: in std_logic;
		output: out std_logic_vector(3 downto 0);
end counter;

architecture behavioral of counter is
   signal temp: std_logic_vector(3 downto 0);
	begin process(CLK)
	begin
		if(CLK'event and CLK='1') then
			temp <= (temp + 1);
			end if;
	end process;
	output <= temp;
end behavioral;