Adding two registers A and B in vhdl

Discussion in 'VHDL' started by Haai, Aug 18, 2007.

  1. Haai

    Haai

    Joined:
    Aug 18, 2007
    Messages:
    3
    I created two registers (A and B), I want to add them together and store the answer in A.
    Is it possible to use operators such as + - x?
    Can any body help me to accomplish this task?

    library ieee;
    use ieee.std_logic_1164.all;

    entity toets3 is
    port(
    data : in std_ulogic_vector(7 downto 0);
    clk : in std_logic;
    Q : out std_ulogic_vector(7 downto 0));
    end toets3;

    architecture a of toets3 is
    signal A,B : std_ulogic_vector (7 downto 0);

    begin
    process (clk)
    begin
    if rising_edge(clk) then
    A <= A + B;
    end if;
    end process;
    Q <= A;
    end a;
     
    Haai, Aug 18, 2007
    #1
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