Again the synthetize problems, structures

Discussion in 'VHDL' started by Pedro Claro, Jul 15, 2003.

  1. Pedro Claro

    Pedro Claro Guest

    Greetings,

    Again I have synthetize problems in my project. This time it gives me
    an
    error and I think it's because of the structure I use.

    entity sched_queues is
    Port ( data_in: in std_logic_vector(7 downto 0);
    queue_nr_in: in std_logic_vector(7 downto 0);
    enqueue: in std_logic;
    main_clk: in std_logic;
    packet_ready: in std_logic;
    packet_size: in std_logic_vector(15 downto 0);
    data_in_clk: out std_logic;
    enq_sucess: out std_logic;
    enq_fail: out std_logic;
    transf_done: out std_logic;
    empty_flags: out std_logic_vector(N_QUEUES-1 downto 0);
    data_out: out std_logic_vector(7 downto 0);
    data_out_clk: in std_logic;
    queue_nr_out: in std_logic_vector(7 downto 0);
    sched_done: in std_logic);
    end sched_queues;

    architecture Behavioral of sched_queues is

    begin

    prQueues: process(main_clk)

    type PACKSZ is array (MAX_SLOTS-1 downto 0) of std_logic_vector(15
    downto 0);

    type FILA is
    record
    mem_addr_start: std_logic_vector(31 downto 0);
    used_slots: std_logic_vector(7 downto 0);
    allowed_slots: std_logic_vector(7 downto 0);
    head_slot: std_logic_vector(7 downto 0);
    packet_size: PACKSZ;
    end record;

    type QUEUES is array(N_QUEUES-1 downto 0) of FILA;

    variable QUEUE: QUEUES;
    variable slot_n: std_logic_vector(7 downto 0);
    variable queue_idx: integer range 0 to 255:=0;
    variable data_transfer_in: std_logic;
    variable counter_in:integer range 0 to 65535;
    variable queue_out_idx:std_logic_vector(7 downto 0);
    variable counter_out: integer range 0 to 65535;
    variable slot_n_out: std_logic_vector(7 downto 0);
    -- signal last values
    variable enqueue_last: std_logic;

    begin


    if(main_clk'event and main_clk='1') then

    if(enqueue_last='0' and enqueue='1') then
    queue_idx:= conv_integer(queue_nr_in);
    if(queue_idx < N_QUEUES ) then
    if(QUEUE(queue_idx).used_slots < QUEUE(queue_idx).allowed_slots)
    then
    slot_n:= conv_std_logic_vector(conv_integer(QUEUE(queue_idx).head_slot
    + QUEUE(queue_idx).used_slots) rem
    conv_integer(QUEUE(queue_idx).allowed_slots),8);
    QUEUE(queue_idx).used_slots:=QUEUE(queue_idx).used_slots+1;
    counter_in:=0;
    data_transfer_in:='1';
    enq_sucess<='0';
    enq_fail<='0';
    else
    enq_fail<='1';
    enq_sucess<='0';
    end if;
    else
    enq_fail<='1';
    enq_sucess<='0';
    end if;
    end if;
    if(enqueue='0') then
    enqueue_last:='1';
    end if;

    end if;

    end process prQueues;

    end Behavioral;

    The errors are:

    WARNING:Xst:790 - C:/Utils/5ano/Projecto/vhdl/scheduller/sched_queues.vhd
    line 68: Index value(s) does not match array range, simulation
    mismatch.
    WARNING:Xst:790 - C:/Utils/5ano/Projecto/vhdl/scheduller/sched_queues.vhd
    line 68: Index value(s) does not match array range, simulation
    mismatch.
    WARNING:Xst:790 - C:/Utils/5ano/Projecto/vhdl/scheduller/sched_queues.vhd
    line 69: Index value(s) does not match array range, simulation
    mismatch.
    WARNING:Xst:790 - C:/Utils/5ano/Projecto/vhdl/scheduller/sched_queues.vhd
    line 69: Index value(s) does not match array range, simulation
    mismatch.
    WARNING:Xst:790 - C:/Utils/5ano/Projecto/vhdl/scheduller/sched_queues.vhd
    line 69: Index value(s) does not match array range, simulation
    mismatch.
    ERROR:Xst:1551 - C:/Utils/5ano/Projecto/vhdl/scheduller/sched_queues.vhd
    line 69: Operator <REMAINDER> must have constant operands or second
    operand must be power of 2

    well, that remainder I must fix it. But it seems that it doesnt like
    to have the 2nd operand being a member of a structure.

    Can anyone help me here?
    Pedro Claro, Jul 15, 2003
    #1
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  2. Pedro Claro

    Pedro Claro Guest

    Sorry about that " types inside the process". I was a mistake.
    Of course you are right, i meant if it alright to have them outside, in
    a package.
    And by the way how can we initiation an array of structures?
    Can we have something like:

    if(init=0) then
    for i in 0 to ARRAY_LIMIT loop
    STRUCT_ARRAY(i).MEMBER_X := something
    -- etc.
    init:='1';
    end loop
    else
    if(rising_edge(clock) then

    -- main_program

    end if
    end if;

    I mean that variable init counts as a somesort of reset, but it's not a signal.
    Pedro Claro, Jul 16, 2003
    #2
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  3. Pedro Claro wrote:


    > You like it?


    Don't get too excited until you have a vhdl testbench working.
    There are really only two types of designs:
    those that work on the board and those that don't.

    > And by the way how can we initiation an array of structures?
    > Can we have something like:
    >
    > if(init=0) then
    > for i in 0 to ARRAY_LIMIT loop
    > STRUCT_ARRAY(i).MEMBER_X := something
    > -- etc.


    Something like that would work.

    I prefer using an array aggregate to define constants.
    For the example code, that would be something like

    constant pack_init : packsz := (others => (others => '0'));
    constant array_init : queues :=
    (others => ( mem_addr_start => x"00000000",
    used_slots => x"00",
    allowed_slots => x"00",
    head_slot => x"00",
    packet_size => pack_init)
    );

    Get yourself a copy of Ashenden. You're going to need it.


    -- Mike Treseler
    Mike Treseler, Jul 16, 2003
    #3
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