Alias problem

Discussion in 'VHDL' started by korte, Dec 7, 2009.

  1. korte

    korte

    Joined:
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    I would like to define an array.
    16-bit 32-bit elements.
    This works well.

    I would like to name the first 8 elements in the array to another array of items, and other elements of an array of registers.

    Code (Text):

    type ARR is array (15 downto 0) of std_logic_vector(31 downto 0);
    signal regs : ARR;

    alias  w: ARR is regs(7 downto 0);
    alias aa: is regs(8);
    alias ab: is regs(9);
    alias ac: is regs(10);
    .
    .
    alias ag: is regs(15);

     
     
    korte, Dec 7, 2009
    #1
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