alliance how?

[Francesco Gadaleta]

I've surfed the Net and i've seen alliance is the set of tools for
my porpouse (school).
But is it a graphic tool?
I've visited the home page but understood a bit, really.
If there is someone who uses alliance , pls can answer?
tnx again
FG

 

[Tuukka Toivonen]

I've surfed the Net and i've seen alliance is the set of tools for
my porpouse (school).
But is it a graphic tool?

I evaluated it briefly, but didn't then start using it because the VHDL
cababilities were a bit inferior.

Yes, some of the Alliance tools use GUI (not all). If I remember correctly,
there was at least silicon layout editor that was graphical. But I don't think
that is very useful in practical work, most people are using VHDL synthesis
programs that directly generate the layout.

Alliance directs users first to describe logic behaviour with very simplified
VHDL syntax. Then the layout is created by hand and the netlist is generated
from it.

The netlist is compared to the behavioral description to see if they match, but
since one can't generated automatically from the other, it's double work which
I don't find making much sense.

My description might not be completely accurate, since it's long time ago I
tried it, so correct me if I have mistaken.

You should also try out "Electric". http://www.staticfreesoft.com
I found this much more easier to use and useful, although it doesn't
support much VHDL either (just very simple netlist syntax).

Coding VHDL textually is, by the way, much more powerful than using
graphical CAD tools.

 

[Francesco Gadaleta]

I evaluated it briefly, but didn't then start using it because the VHDL
cababilities were a bit inferior.

Yes, some of the Alliance tools use GUI (not all). If I remember correctly,
there was at least silicon layout editor that was graphical. But I don't think
that is very useful in practical work, most people are using VHDL synthesis
programs that directly generate the layout.

Alliance directs users first to describe logic behaviour with very simplified
VHDL syntax. Then the layout is created by hand and the netlist is generated
from it.

The netlist is compared to the behavioral description to see if they match, but
since one can't generated automatically from the other, it's double work which
I don't find making much sense.

My description might not be completely accurate, since it's long time ago I
tried it, so correct me if I have mistaken.

You should also try out "Electric". http://www.staticfreesoft.com
I found this much more easier to use and useful, although it doesn't
support much VHDL either (just very simple netlist syntax).

Coding VHDL textually is, by the way, much more powerful than using
graphical CAD tools.

tnx very much.
I've read alliance manuals (about simulation and synthesis) and
installed emacs vhdl mode (not the compiler).
I think this could be useful for my porpouses.
But if i had other doubts i'll ask you (or someone else)how to resolve
them.
Tnx again.
FG