Ambiguous reference to type

[jahaya]

Hello all,

I was trying to complie the following code. I need one bit at each
rising edge frm the constant std_logic_vector and afterward i am
rotating it left in cyclic way.

But,I got an error " Ambiguous reference to type "UNSIGNED" ". I didnt
understand what it is meant , secondly can anyone suggest me how to
assign std_logic_vector to unsiged and vice versa.any type conv ?

regards,
Ali
-----------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_lOGIC_1164.ALL;
USE IEEE.NUMERIC_BIT.ALL;
USE IEEE.NUMERIC_STD.ALL;

ENTITY SHIFT_REG IS
PORT
(
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
OUTPUT : OUT STD_LOGIC
);
END SHIFT_REG;

ARCHITECTURE ARCH_REG OF SHIFT_REG IS

CONSTANT DATA_IN : UNSIGNED(7 DOWNTO 0) := "01010101";

BEGIN

INP: PROCESS(CLK,RESET)

VARIABLE DATAV_IN1 : UNSIGNED(7 DOWNTO 0);
VARIABLE DATAV_IN2 : UNSIGNED(7 DOWNTO 0);


BEGIN
IF (RESET = '0') THEN
OUTPUT <= '0';
DATAV_IN1 := DATA_IN;
ELSIF (CLK'EVENT AND CLK = '1') THEN
OUTPUT <= DATAV_IN1(7);
DATAV_IN2 := ROTATE_LEFT (DATAV_IN1,1);
DATAV_IN1 := DATAV_IN2;

END IF;
END PROCESS INP;

END ARCHITECTURE ARCH_REG;
-----------------------------------------------------------

 

[Hubble]

You should only use one of numeric_std and numeric_bit. Both packages
define the type "unsigned" differently.
numeric_bit:
type unsigned is array (natural range <>) of bit;
numeric_std:
type unsigned is array (natural range <>) of std_logic;

You instructed the compiler to use (!) all (!) symbols in both
packages.

Delete "use ieee.numeric_bit.all" (obviously unused) and everything
should be ok. You can also specify "ieee.numeric_std.unsigned" in each
place where you use unsigned.

Most design units only need either numeric_bit or numeric_std. If you
really need symbols of both packages, you must qualify them and not use
a "use package.all" statement.

Hubble.

 

[jahaya]

Hi hubble,

it works now !

thank u

regards,
ahmed