array ar data type in port in vhdl entity

[lea]

I am trying to input an image,that is in form of a matrix consisting of integers in the range 0-255 in an entity in order to perform some operations on it for the filtering. I am quite new to hdl and i am confused whether it is possible to have an array as data type to a port?

i mean something like this:

entity block is
port(
my_array: in array( 7 downto 0);
clk: in bit);
end block;

 

[JohnDuq]

Think of a port as a physical entity, like a I/O pin on a FPGA. The pin itself doesn't have any type of matrix capability. You need to add the matrix capability around it.

For example, you could have an array of three bytes come in on 24 pins:

my_array(0) <= p1 & p2 & p3 & p4 & p5 & p6 & p7 & p8;
my_array(1) <= p9 & p10 & p11 & p12 & p13 & p14 & p15 & p16;
my_array(2) <= p17 & p18 & p19 & p20 & p21 & p22 & p23 & p24;

Another example is to bring in the data one byte at a time in a serial manner:

process get_my_data(byte_clk)

signal: index : std_logic_vector = 0;

begin
if byte_clk'event and byte_clk = '1' then
my_data(index) <= p1 & p2 & p3 & p4 & p5 & p6 & p7 & p8;
index := index + 1;
end if;
end; -- process

(yes everyone, I know this isn't great code because index isn't bounded, but it is just a quick example)

Have fun learning VHDL!

John

 

[vipinlal]

you can give an array as an input or output of module.its totally fine.even custom made types are allowed as an input / output to module.see more about data types at vhdlguru.blogspot.com/2010/03/some-useful-vhdl-data-types.html
also abt arrays check this link :
vhdlguru.blogspot.com/2010/02/arrays-and-records-in-vhdl.html