Association list in component instantiations

Discussion in 'VHDL' started by Thomas Heller, Jan 30, 2011.

  1. I do not understand what I can use in the association list of a
    component instantiation. Say, I have a component declaration like this:

    entity spislave is
    Port ( sysclock : in STD_LOGIC;
    data_out : out STD_LOGIC_VECTOR(7 downto 0);
    data_strobe : out STD_LOGIC;
    sclk : in STD_LOGIC;
    mosi : in STD_LOGIC;
    cs : in STD_LOGIC);
    end spislave;

    Then a typical instantiation is:

    U1: spislave PORT MAP(
    sysclock => clk64,
    data_out => spi_data,
    data_strobe => spi_strobe,
    sclk => spi_clk,
    mosi => spi_mosi,
    cs => spi_cs
    );

    If I want to connect the data_out signal to parts of a databus then
    I cannot write
    data_out => data_bus(7 downto 0),
    although I can write
    sclk => not pin_7;

    Can someone point me to a reference that explains which kind of 'things'
    I can use in the instantiation?

    Thanks,
    Thomas
     
    Thomas Heller, Jan 30, 2011
    #1
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  2. On Sun, 30 Jan 2011 19:25:38 +0100, Thomas Heller wrote:

    >I do not understand what I can use in the association list of a
    >component instantiation. Say, I have a component declaration like this:
    >
    >entity spislave is
    > Port ( sysclock : in STD_LOGIC;
    > data_out : out STD_LOGIC_VECTOR(7 downto 0);
    > data_strobe : out STD_LOGIC;
    > sclk : in STD_LOGIC;
    > mosi : in STD_LOGIC;
    > cs : in STD_LOGIC);
    >end spislave;
    >
    >Then a typical instantiation is:
    >
    > U1: spislave PORT MAP(
    > sysclock => clk64,
    > data_out => spi_data,
    > data_strobe => spi_strobe,
    > sclk => spi_clk,
    > mosi => spi_mosi,
    > cs => spi_cs
    > );
    >
    >If I want to connect the data_out signal to parts of a databus then
    >I cannot write
    > data_out => data_bus(7 downto 0),


    Why not? Works for me. Who's complaining? Did you *really*
    say (7 downto 0), or was there something non-static going on
    in your slice range?

    >although I can write
    > sclk => not pin_7;


    That's slightly different; the actual association can be
    any monadic function of a signal. This was done to allow
    for type conversions in the port map, but it works for
    any monadic function and the "not" operator is, of course,
    nothing more than the monadic function
    function "not"(v: in std_logic) return std_logic;

    >Can someone point me to a reference that explains which kind of 'things'
    >I can use in the instantiation?


    For an input port:
    signals or slices thereof; expressions yielding a constant value.
    For an output or inout port:
    signals or slices thereof.
    Conversion functions can be applied: they must be monadic,
    and the syntax is different for input and output ports:

    port map (some_input => F1(in_sig),
    F2(some_output) => out_sig,
    F3out(some_inout) => F3in(io_sig))

    The actual must be a "static name" but that should be OK...

    In VHDL-2008 you can put arbitrary expressions to an input port,
    but your port will suffer an added delta cycle delay from the
    implied process that computes the expression.

    --
    Jonathan Bromley
     
    Jonathan Bromley, Jan 30, 2011
    #2
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  3. Am 30.01.2011 22:09, schrieb Jonathan Bromley:
    > On Sun, 30 Jan 2011 19:25:38 +0100, Thomas Heller wrote:
    >
    >> I do not understand what I can use in the association list of a
    >> component instantiation. Say, I have a component declaration like this:
    >>
    >> entity spislave is
    >> Port ( sysclock : in STD_LOGIC;
    >> data_out : out STD_LOGIC_VECTOR(7 downto 0);
    >> data_strobe : out STD_LOGIC;
    >> sclk : in STD_LOGIC;
    >> mosi : in STD_LOGIC;
    >> cs : in STD_LOGIC);
    >> end spislave;
    >>
    >> Then a typical instantiation is:
    >>
    >> U1: spislave PORT MAP(
    >> sysclock => clk64,
    >> data_out => spi_data,
    >> data_strobe => spi_strobe,
    >> sclk => spi_clk,
    >> mosi => spi_mosi,
    >> cs => spi_cs
    >> );
    >>
    >> If I want to connect the data_out signal to parts of a databus then
    >> I cannot write
    >> data_out => data_bus(7 downto 0),

    >
    > Why not? Works for me. Who's complaining? Did you *really*
    > say (7 downto 0), or was there something non-static going on
    > in your slice range?


    I was confused. Of course it works.

    What I really want and what didn't work is connecting some bits of an
    input signal on the component (say, the data bus of an ADC) to a signal,
    and other bits to a constant. Example:

    X: myinstance PORT MAP(
    ...
    data_input => data_bus(7 downto 0) & "00000000",
    ...)

    Is it possible to implement this without using another signal, like this:

    adc_datainput <= data_bus(7 downto 0) & "00000000";
    X: myinstance PORT MAP(
    ...
    data_input => adc_input,
    ...)


    >> although I can write
    >> sclk => not pin_7;

    >
    > That's slightly different; the actual association can be
    > any monadic function of a signal. This was done to allow
    > for type conversions in the port map, but it works for
    > any monadic function and the "not" operator is, of course,
    > nothing more than the monadic function
    > function "not"(v: in std_logic) return std_logic;
    >
    >> Can someone point me to a reference that explains which kind of 'things'
    >> I can use in the instantiation?

    >
    > For an input port:
    > signals or slices thereof; expressions yielding a constant value.
    > For an output or inout port:
    > signals or slices thereof.
    > Conversion functions can be applied: they must be monadic,
    > and the syntax is different for input and output ports:
    >
    > port map (some_input => F1(in_sig),
    > F2(some_output) => out_sig,
    > F3out(some_inout) => F3in(io_sig))
    >
    > The actual must be a "static name" but that should be OK...
    >
    > In VHDL-2008 you can put arbitrary expressions to an input port,
    > but your port will suffer an added delta cycle delay from the
    > implied process that computes the expression.
    >


    Thanks for this useful info,
    Thomas
     
    Thomas Heller, Feb 3, 2011
    #3
  4. On Thu, 03 Feb 2011 21:49:58 +0100, Thomas Heller wrote:

    >What I really want and what didn't work is connecting some bits of an
    >input signal on the component (say, the data bus of an ADC) to a signal,
    >and other bits to a constant. Example:
    >
    >X: myinstance PORT MAP(
    > ...
    > data_input => data_bus(7 downto 0) & "00000000",
    > ...)
    >
    >Is it possible to implement this without using another signal


    Only in VHDL-2008, as far as I'm aware.

    Have you tried

    data_input(15 downto 8) => data_bus(7 downto 0),
    data_input(7 downto 0) => "00000000"

    ??? I know you can do that to split a vector port out to
    several different signals, but I'm not sure whether it's
    legal to mix constants and signals in that way.
    --
    Jonathan Bromley
     
    Jonathan Bromley, Feb 3, 2011
    #4
  5. Am 03.02.2011 22:38, schrieb Jonathan Bromley:
    > On Thu, 03 Feb 2011 21:49:58 +0100, Thomas Heller wrote:
    >
    >> What I really want and what didn't work is connecting some bits of an
    >> input signal on the component (say, the data bus of an ADC) to a signal,
    >> and other bits to a constant. Example:
    >>
    >> X: myinstance PORT MAP(
    >> ...
    >> data_input => data_bus(7 downto 0)& "00000000",
    >> ...)
    >>
    >> Is it possible to implement this without using another signal

    >
    > Only in VHDL-2008, as far as I'm aware.
    >
    > Have you tried
    >
    > data_input(15 downto 8) => data_bus(7 downto 0),
    > data_input(7 downto 0) => "00000000"
    >
    > ??? I know you can do that to split a vector port out to
    > several different signals, but I'm not sure whether it's
    > legal to mix constants and signals in that way.


    Seems to work. Cool!

    Thanks,
    Thomas
     
    Thomas Heller, Feb 4, 2011
    #5
  6. Thomas Heller

    rickman Guest

    On Jan 30, 4:09 pm, Jonathan Bromley <>
    wrote:
    >
    > That's slightly different; the actual association can be
    > any monadic function of a signal.


    Why did you use the term "monadic" rather than "unary"? Do I
    misunderstand the meaning of either or both? It took me five minutes
    to find a simple definition of "monadic function". That may sound
    like a pretty short time, but when was the last time you spent five
    minutes looking for a word definition? "Unary" is a much more common
    term and I think more clear in this context unless there is some
    useful connotation to "monadic" I don't appreciate.

    Rick
     
    rickman, Feb 4, 2011
    #6
  7. On Fri, 4 Feb 2011 08:25:11 -0800 (PST), rickman wrote:

    >Why did you use the term "monadic" rather than "unary"?


    Thanks - that's a bit of jargon that I must have
    incorrectly absorbed from somewhere. Now you've
    provoked me into looking, I see that it's not even
    strictly correct, at least not if you're a
    mathematician or a (Haskell-style) functional
    programmer. As you may guess, I am neither.

    (Side note: some programming languages do tend to
    use "monadic" and "dyadic" (and even "variadic")
    to describe the number of arguments of a function.
    APL is certainly one such. Maybe they're wrong too.)

    > "Unary" is a much more common term


    And rigorously accurate too. The style-checker
    in my head (which usually serves me tolerably well)
    has no problem with "unary operator", but finds
    the sound of "unary function" rather strange.
    Time for a re-calibrate, maybe.

    Ho hum. Still getting things wrong after all
    these years :-(
    --
    Jonathan Bromley
     
    Jonathan Bromley, Feb 4, 2011
    #7
  8. Thomas Heller

    Andy Guest

    On Feb 4, 1:24 pm, Jonathan Bromley <>
    wrote:
    > The style-checker
    > in my head (which usually serves me tolerably well)
    > has no problem with "unary operator", but finds
    > the sound of "unary function" rather strange.
    > Time for a re-calibrate, maybe.


    I agree, unary more commonly applies to operators with only one
    operand. While all operators are functions (in vhdl), not all
    functions are operators, and perhaps that would be a/the problem.
    Would "unary function" imply a function that was invoked as a unary
    operator?

    What what would be the term for a function with zero arguments?
    Nonadic? ;^)

    OK, I did not look up monadic, but I took a lucky guess... and I knew
    what dyadic meant, which helped a lot.

    Andy
     
    Andy, Feb 7, 2011
    #8
  9. Thomas Heller

    rickman Guest

    On Feb 7, 1:29 pm, Andy <> wrote:
    > On Feb 4, 1:24 pm, Jonathan Bromley <>
    > wrote:
    >
    > > The style-checker
    > > in my head (which usually serves me tolerably well)
    > > has no problem with "unary operator", but finds
    > > the sound of "unary function" rather strange.
    > > Time for a re-calibrate, maybe.

    >
    > I agree, unary more commonly applies to operators with only one
    > operand. While all operators are functions (in vhdl), not all
    > functions are operators, and perhaps that would be a/the problem.
    > Would "unary function" imply a function that was invoked as a unary
    > operator?
    >
    > What what would be the term for a function with zero arguments?
    > Nonadic? ;^)
    >
    > OK, I did not look up monadic, but I took a lucky guess... and I knew
    > what dyadic meant, which helped a lot.
    >
    > Andy


    Maybe you should have looked up Nonadic...

    nonadic (comparative more nonadic, superlative most nonadic)

    1. of or pertaining to an nonad; ninefold


    Rick
     
    rickman, Feb 8, 2011
    #9
  10. Thomas Heller

    rickman Guest

    On Feb 7, 1:29 pm, Andy <> wrote:
    > On Feb 4, 1:24 pm, Jonathan Bromley <>
    > wrote:
    >
    > > The style-checker
    > > in my head (which usually serves me tolerably well)
    > > has no problem with "unary operator", but finds
    > > the sound of "unary function" rather strange.
    > > Time for a re-calibrate, maybe.

    >
    > I agree, unary more commonly applies to operators with only one
    > operand. While all operators are functions (in vhdl), not all
    > functions are operators, and perhaps that would be a/the problem.
    > Would "unary function" imply a function that was invoked as a unary
    > operator?
    >
    > What what would be the term for a function with zero arguments?
    > Nonadic? ;^)
    >
    > OK, I did not look up monadic, but I took a lucky guess... and I knew
    > what dyadic meant, which helped a lot.
    >
    > Andy


    Or maybe you should have looked up "unary function"?

    Rick
     
    rickman, Feb 8, 2011
    #10
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