Asynchronous Tri-state Bus in VHDL (I/O): optimizing for CPLD design.

Discussion in 'VHDL' started by D0tcom, Jan 28, 2011.

  1. D0tcom

    D0tcom

    Joined:
    Jan 27, 2011
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    For an assignment i'm coding three different CPLD's, due to their size and the fact that 2 of them don't receive a clock signal I've run into some trouble.


    Problem 1:

    I want to code an I/O bus (with tristate) in a CPLD without a clock_in.
    This is what i've come up so far.
    ---------------------------------------------------------------------
    AD: inout std_logic_vector (7 downto 0);
    Analog_Mux: out std_logic_vector(11 downto 0)

    signal Count24: std_logic_vector(23 downto 0);

    if(AD_EN = '0') then
    Analog_Mux <= "ZZZZZZZZZZZZ";
    AD <= "ZZZZZZZZ";
    else
    if(AD_RD = '1') then
    if(Count_2_Low_RD = '1') then
    AD <= Count24(7 downto 0);
    elsif(Count_2_Mid_RD = '1') then
    AD <= Count24(15 downto 8);
    elsif(Count_2_High_RD = '1') then
    AD <= Count24(23 downto 16);
    else
    AD <= "--------";
    end if;
    elsif(AD_WR = '1') then
    if(Mux12_WR = '1') then
    Analog_Mux(7 downto 0) <= AD;
    elsif(Mux3_WR = '1') then
    Analog_Mux(11 downto 8) <= AD(3 downto 0);
    else
    Analog_Mux <= "------------";
    end if;
    end if;

    end if;

    The problem is, that the synthesiser translates this in some sort of latching sequence. The select signals are mutually exclusive (due to their source origins)

    Any tips on how to get a stable solution to this would greatly be appreciated!




    Problem 2:

    On a different CPLD I need to implement a 24bits timer (output is an enablesignal WindowBusy), that is to be programmed (ThreshHold filled via AD) via an 8-bits bus(AD). Below is the code.

    lbl2: process(StartWindow,Clock)
    begin
    if(StartWindow = '0')then
    WindowBusy <= '0';
    window <= ThreshHold;
    else
    if(Clock'event and Clock = '1') then
    if(window = "000000000000000000000000") then
    WindowBusy <='0';
    else
    window <= window - "000000000000000000000001";
    WindowBusy <= '1';
    end if;
    end if;
    end if;
    end process;

    lbl3_AD: process(Clock,N_Reset)
    begin
    if(Clock'event and Clock = '1') then
    if(Window_Low_WR = '1') then
    ThreshHold(7 downto 0)<= AD;
    elsif(Window_Mid_WR = '1') then
    ThreshHold(15 downto 8)<= AD;
    elsif(Window_High_WR ='1') then
    ThreshHold(23 downto 16) <= AD;
    else
    ThreshHold <= ThreshHold;
    end if;
    end if;
    end process;

    This code synthesizes fine. but it generates a lot of logical functions. The chip I want too implement this on only has room for 64 of those! Does anyone have tips too reduce logical size while retaining functionality?

    Any help would be greatly appreciated!

    Sincerely,
     
    D0tcom, Jan 28, 2011
    #1
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