Available: Open Source VHDL parser - for free

[Sumit Gupta]

Hi all

I wrote a VHDL parser as part of another larger software tool about 6
years ago. The webpage, on which the parser is, is going to be
retired soon. So, if anyone is interested, here is a link to my
parser:

http://www.cecs.uci.edu/~iesag/oldPage/Topts/

Regards
Sumit

 

[Kelvin]

Got any Verilog parser?

Kelvin

 

[Phil Tomson]

Got any Verilog parser?

Check out Icarus Verilog:

http://www.icarus.com/eda/verilog/

Phil

 

[jalil]

I have a hyperlinked VHDL syntax which might be usefull when creating a parser at http://www.jalilweb.com/content/view/37/35/

 

[hassen07]

Hi,

Has anyone the VHDL parser mentioned above ? I need one for my master researchs.


Thanks in advance.

 

[QuestaTechnologies]

There is an excellent free verilog parser in Java can be downloaded from questatechnologies.com/Verilog-RTL-Parser.html . Similarly the VHDL parser can be downloaded from questatechnologies.com/VHDL-RTL-Parser.html .

There are many other utlities like RTL sorting, Design browser, IP integration for SoC, entire suit of such free utilities can be found at questatechnologies.com