Basic question

[m]

Forgive me for asking something very basic. I bought two books on
VHDL and they just jump in and use this terminology without explaning
what it does. Also, I come from ten years of Verilog (I come in
peace).

signal A : unsigned( 7 downto 0);
..
..
..
A <= (others => '0');


My guess is that (others => '0') simply assigns hex 00 to A.


Why can't or wouldn't one just say "A <= '0';" or something similarly
simple?
Why is "others" required?


Thank you,


-Martin

 

[JohnSmith]

Forgive me for asking something very basic. I bought two books on
VHDL and they just jump in and use this terminology without explaning
what it does. Also, I come from ten years of Verilog (I come in
peace).

signal A : unsigned( 7 downto 0);
.
.
.
A <= (others => '0');

My guess is that (others => '0') simply assigns hex 00 to A.

Why can't or wouldn't one just say "A <= '0';" or something similarly
simple?
Why is "others" required?

Thank you,

-Martin

When "A" is declared to std_logic, " A <= '0'; " is correct. You have
declared A to an array,
"others" is for filling complex objects, like arrays. Yo may write " A
<= "00000000"; " also.
"others" is useful when the number of elements in array are changing

For example when you'd like to change to declaration to unsigned(8
downto 0) and you are using others, don't need to change " A <=
(others=>'0')" line, anyway need to write " A <= "000000000"; ", so
you dont need to change the code when you are using others.

J

 

[m]

Thank you. Very helpful explanations. Just trying to get my head
around VHDL as I have to work some some code and translate it into
Verilog for my project.

Any suggestions on a book/books that might fill-in the gaps. I
purchased the following titles:

"FPGA prototyping by VHDL examples. Xilinx Spartan-3 Version" by Pong
P. Chu
"Circuit design with VHDL" by Volnei A. Pedroni

I was surprised that neither book covered this basic (others => x)
construct. They go ahead and start using it by the second or third
example with no explanation whatsoever. If you come from --forgive
me-- "conventional" languages, VHDL can look very cryptic. I would
think that an introductory book would be careful about not using new
constructs until they are addressed in the text. Perhaps I bought the
wrong books?
Thanks,

-Martin

 

[Guest]

A <= X"00"; -- will work, until you change the size of A.

Right. But please note that X"00" actually gets translated
(lexically substituted) into "00000000", four 0s for each
0 in the hex value. So when using X"...." you MUST be
creating a value with 4N elements. Tedious but true.

A <= "0000_0000"; -- will work, ditto,
-- the '_' is optional but keeps you from getting lost

Sorry to nit-pick, but I don't think that's true.
In plain double-quotes like that, you have a 9-element
string which can only translate into a 9-element vector
of some enumeration type that has '0' and '_' in its
set of available literals. The latter is illegal for
std_logic. By contrast, B"0000_0000" will work
in the way you suggest, because of the way the
lexical substitution is defined to operate.

It's all a bit tiresome, but very consistent

I'm not using my normal news service so may have missed
some posts, but I hope someone has also pointed out to
the OP that it may be better to write

result <= std_logic_vector(to_unsigned(0, result'length));

(depending on what he's trying to do) although that
requires you to add

use ieee.numeric_std.all;

to the context clauses.

 

[Kevin Neilson]

Forgive me for asking something very basic. I bought two books on ....

Why can't or wouldn't one just say "A <= '0';" or something similarly
simple?

Short answer: VHDL is overly strict, and 'simple' can rarely be used to
describe its syntax. Coming from the Verilog world, you might find this
annoying. -Kevin

 

[Andy]

I'm not using my normal news service so may have missed
some posts, but I hope someone has also pointed out to
the OP that it may be better to write

  result <= std_logic_vector(to_unsigned(0, result'length));

Since the OP was assigning a vector of type unsigned (assuming
numeric_std.unsigned), it would be better for him to write:

a <= to_unsigned(0, a'length);

Or if you are typographically challenged and hoping the synthesis tool
will be kind to you:

a<=a-a;

uses only 5 keys and 7 characters ;^)

Andy

 

[Svenn Are Bjerkem]

"FPGA prototyping by VHDL examples. Xilinx Spartan-3 Version" by Pong
P. Chu
"Circuit design with VHDL" by Volnei A. Pedroni

I was surprised that neither book covered this basic (others => x)
construct. They go ahead and start using it by the second or third
example with no explanation whatsoever. If you come from --forgive

I got the Pedroni book, too, and found it irritating that he didn't
take time to explain it. As we see from this thread, it doesn't take
many words to explain what the others clause is and how it works.
Pedroni does give more examples of the use of others in his book than
other authors, and they are listed in the index, which is not so
common in other books.

I am struggling to try to solve a problem that I think is related so
I'll throw it in here: I want to write a module using generics to
configure different sizes of a std_logic array where each signal in
the array is anded with one single mask bit.

signal chip_en : std_logic_vector(g_ndevices-1 downto 0); -- active
low
signal unmask_chip_en : std_logic;

debug(12 downto 9) <= "1111" and chip_en and unmask_chip_en;

Rtlvision from Concept Engineering accepts the assignment and shows
logic doing what I want to do: and'ing each bit of chip_en with
unmask_chip_en for all cases of g_ndevice. If g_ndevice is smaller
than 4, the unassigned bits in debug(12 downto 9) is set to 1.
This doesn't help me as Xilinx XST complains that the sizes of the
signals have to be the same. Is there a simple way to solve this, or
will I have to use if/then/elsif for each of the possibilities in
g_ndevice?