Beginner Help

Discussion in 'VHDL' started by Linas Petras, Sep 23, 2004.

  1. Linas Petras

    Linas Petras Guest

    Just wondered if anyone who be so kind to translate the following bit of
    psuedo verilog to vhdl.

    As I've just started VDHL, trying to understand Verilog is just a bit much
    for me :-(

    Linas

    PS This is NOT a school project
    --------------------------------------------------------------
    SUBDESIGN glue
    (
    pci_clk, LP_RW, nCS : INPUT;
    nRE, nWE : OUTPUT;
    )

    VARIABLE
    Q[2..0] : DFF;

    BEGIN
    Q[].clk = pci_clk;
    Q[].prn = NOT nCS;
    Q[0].d = nCS;
    Q[1].d = Q[0].q;
    Q[2].d = Q[1].q;
    nRE = nCS OR NOT LP_RW OR NOT Q[2].q;
    nWE = nCS OR LP_RW OR NOT Q[1].q;
    END

    ---------------------------
     
    Linas Petras, Sep 23, 2004
    #1
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  2. Linas Petras

    Jim Lewis Guest

    Linas,
    Looks more like AHDL to me with three registers in the design.
    Don't know AHDL well, but this is what I think I see.

    > Q[].clk = pci_clk; --- Clock for all registers
    > Q[].prn = NOT nCS; --- set for all registers / ?Sync or Async?
    > Q[0].d = nCS; --- Input to register 0 gets nCS
    > Q[1].d = Q[0].q; --- Input to register 1 gets output from register 0
    > Q[2].d = Q[1].q; --- Input to register 2 gets output from register 1


    -- Logic. Q[1].q and Q[2].q are the outputs of registers 1 and 2 respectively.
    > nRE = nCS OR NOT LP_RW OR NOT Q[2].q;
    > nWE = nCS OR LP_RW OR NOT Q[1].q;


    Have Fun.

    Jim



    --
    ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
    Jim Lewis
    Director of Training mailto:
    SynthWorks Design Inc. http://www.SynthWorks.com
    1-503-590-4787

    Expert VHDL Training for Hardware Design and Verification
    ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
     
    Jim Lewis, Sep 23, 2004
    #2
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  3. Linas Petras

    Dan RADUT Guest

    Hi Linas:

    A VHDL translation of your code could be this one:

    library IEEE;
    use IEEE.std_logic_1164.all;

    -- entity glue declaration
    entity glue is
    port ( iPciClk :in std_logic; -- clock input port pci_clk
    iLP_RW :in std_logic; -- LP_RW
    iCSn :in std_logic; -- nCS input, active LOW

    oREn :eek:ut std_logic; -- nRE output, active LOW
    oWEn :eek:ut std_logic ); -- nWE output, active LOW
    end entity glue;

    architecture behav_arch of glue is
    -- declare a signal that corresponds to a 3-dff register
    signal shiftreg_3dff: std_logic_vector(2 downto 0);

    -- declare a signal to invert the iCSn
    signal inv_iCSn: std_logic;

    begin
    -- invert iCSn
    inv_iCSn <= not iCSn;

    -- this process is the code of a 3-dff shift register: its outputs are
    -- asynchronously preset when the chip select input is not active. When
    -- chip select is active the shift register is shifting data, right to left
    -- direction, on the rising edge of the input clock
    shiftreg3dff:process(iPciClk, iCSn)
    begin
    if inv_iCSn = '0' then -- async set of shiftregister outputs
    shiftreg_3dff <= "111";
    elsif rising_edge(iPciClk) then
    shiftreg_3dff(2 downto 1)<= shiftreg_3dff(1 downto 0);
    shiftreg_3dff(0)<= iCSn;
    end if;
    end process;

    -- driving the entity output ports
    oREn <= iCSn or (not iLP_RW) or (not shiftreg_3dff(2));
    oWEn <= iCSn or iLP_RW or (not shiftreg_3dff(1));

    end architecture behav_arch;

    HTH,

    Dan Radut

    "Linas Petras" <> wrote in message news:<citq10$2ubm$>...
    > Just wondered if anyone who be so kind to translate the following bit of
    > psuedo verilog to vhdl.
    >
    > As I've just started VDHL, trying to understand Verilog is just a bit much
    > for me :-(
    >
    > Linas
    >
    > PS This is NOT a school project
    > --------------------------------------------------------------
    > SUBDESIGN glue
    > (
    > pci_clk, LP_RW, nCS : INPUT;
    > nRE, nWE : OUTPUT;
    > )
    >
    > VARIABLE
    > Q[2..0] : DFF;
    >
    > BEGIN
    > Q[].clk = pci_clk;
    > Q[].prn = NOT nCS;
    > Q[0].d = nCS;
    > Q[1].d = Q[0].q;
    > Q[2].d = Q[1].q;
    > nRE = nCS OR NOT LP_RW OR NOT Q[2].q;
    > nWE = nCS OR LP_RW OR NOT Q[1].q;
    > END
    >
    > ---------------------------
     
    Dan RADUT, Sep 24, 2004
    #3
  4. Linas Petras

    Linas Petras Guest

    "Dan RADUT" <> wrote in message
    news:...
    > Hi Linas:
    >
    > A VHDL translation of your code could be this one:
    >
    > ..... stuff deleted .....


    Dan,

    Many thanks, I'll use this as the starting point.

    Linas
     
    Linas Petras, Sep 25, 2004
    #4
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