Both clock edges

Discussion in 'VHDL' started by Steve, Oct 1, 2004.

  1. Steve

    Steve Guest

    I'm designing a simple VHDL system, which is driven by a clock. Is it bad
    practice to use both clock edges in my system.

    The system I'm working on needs to output data, which must be valid while
    the clock is high. So I was thinking I could use the falling edge to set
    everything up. It must also read data, which is also valid while the clock
    is high. To do this, I could use the rising edge.

    For example:

    p1 : process(CLK)
    begin
    if rising_edge(CLK) then
    blah blah blah (read data)
    end if;
    end process p1;


    p2 : process(CLK)
    begin
    if falling_edge(CLK) then
    blah blah blah (write data)
    end if;
    end process p2;


    This would make my job easier, but is it a good way to do things? Most
    examples I have seen tend to use one edge of a clock.
     
    Steve, Oct 1, 2004
    #1
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  2. Steve wrote:

    > I'm designing a simple VHDL system, which is driven by a clock. Is it bad
    > practice to use both clock edges in my system.


    Unless it's truly needed, it's best to avoid it. It usually creates more
    problems than it's solving. For your problem: just precalculate the needed
    values in the previous clock cycle (pipelining your design).

    Regards,

    Pieter Hulshoff
     
    Pieter Hulshoff, Oct 1, 2004
    #2
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  3. Steve

    rickman Guest

    Steve wrote:
    >
    > I'm designing a simple VHDL system, which is driven by a clock. Is it bad
    > practice to use both clock edges in my system.
    >
    > The system I'm working on needs to output data, which must be valid while
    > the clock is high. So I was thinking I could use the falling edge to set
    > everything up. It must also read data, which is also valid while the clock
    > is high. To do this, I could use the rising edge.
    >
    > For example:
    >
    > p1 : process(CLK)
    > begin
    > if rising_edge(CLK) then
    > blah blah blah (read data)
    > end if;
    > end process p1;
    >
    > p2 : process(CLK)
    > begin
    > if falling_edge(CLK) then
    > blah blah blah (write data)
    > end if;
    > end process p2;
    >
    > This would make my job easier, but is it a good way to do things? Most
    > examples I have seen tend to use one edge of a clock.


    Using both edges of the clock is not necessarily a bad practice. It is
    definitely bad for the same signal or variable since it will not
    synthesize. But the way you are using it should be ok... except for one
    thing. The way you have defined your IO signals, you should be clocking
    both input and output on the falling edge. If your input data is is
    valid while the clock is high, then you would have *no* setup time
    clocking on the rising edge. Typically FPGAs have a zero hold time so
    it would be ok to clock on the falling edge.

    I vaguely remember working on a system spec'd by the government this
    way. I thought it odd since it was very unclear how they really wanted
    you to do the job. In the end I took a look at existing systems and
    determined that outputs were clocked on one edge and inputs were clocked
    on the other edge. This clocking compensated for a few ns of skew in
    the cable. The spec said the inputs would be valid while the clock was
    high, but really I needed to analyze the situation. I suggest that you
    do the same.

    --

    Rick "rickman" Collins


    Ignore the reply address. To email me use the above address with the XY
    removed.

    Arius - A Signal Processing Solutions Company
    Specializing in DSP and FPGA design URL http://www.arius.com
    4 King Ave 301-682-7772 Voice
    Frederick, MD 21701-3110 301-682-7666 FAX
     
    rickman, Oct 2, 2004
    #3
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