Checking to see if one second has passed

Discussion in 'VHDL' started by johnnyjohn2009, Dec 6, 2009.

  1. johnnyjohn2009

    johnnyjohn2009

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    Dec 3, 2009
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    Hello,

    This is probably so simple to achieve, but I am unsure how to code this effciently. At the moment I have tried while Clock < 1000 ms. I have also tried .. if the clock is less than 1000 ms..

    I would like to increment a counter while the clock is less than 1 second. Once a second has passed pass the count value to a signal which then goes to the entity output. Then repeat the process.

    If anyone has any ideas i'd be most grateful
    johnnyjohn2009, Dec 6, 2009
    #1
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  2. johnnyjohn2009

    jeppe

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    Denmark
    VHDL code with statements like "while Clock < 1000 ms" will only be useful for simulation - not for synthesizing to hardware.

    What's your goal with the code?
    jeppe, Dec 6, 2009
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  3. johnnyjohn2009

    johnnyjohn2009

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    Dec 3, 2009
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    Hi, many thanks for your reply with this and my other post.

    Just to let you know this is part of my final year project at university so help should be limited!

    My goal is to count pulses 0 -> 1 within a 1 second window repeatedly. Once one second has passed the process should be repeated. My attempt is shown below:

    Process(clock) begin
    timer <= '1', '0' after 1000 ms;

    if timer = '0' then
    FreqCount <= "0000";
    timer <= '1';
    end if;

    if timer = '0' then
    if rising_edge(Clock) then
    if Datain = '1' then
    FreqCount <= FreqCount + "1";
    end if;

    else -- clock event is falling edge 1 -> 0
    if Datain = '1' then
    FreqCount <= FreqCount + "1";
    end if;

    end if;
    TempCount <= FreqCount;
    end if;


    end process;

    FreqOut <= TempCount;
    end Behavioral;
    Last edited: Dec 6, 2009
    johnnyjohn2009, Dec 6, 2009
    #3
  4. johnnyjohn2009

    jeppe

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    Denmark
    Inspiration for a simulation

    Do you have some kind of hardware / FPGA-kit which your planning to use or do you "just" want to make a simulation of the solution.

    Important to know becourse the VHDL code you can use depend on this.

    Take a look at this code - not the solution to your problem - only inspiration.

    Code:
    library IEEE;
    use IEEE.STD_LOGIC_1164.ALL;
    use IEEE.STD_LOGIC_ARITH.ALL;
    use IEEE.STD_LOGIC_UNSIGNED.ALL;
    
    entity Freq_counter1 is
    end Freq_counter1;
    
    architecture Behavioral of Freq_counter1 is
       signal FreqCount, TempCount: std_logic_vector( 3 downto 0) := "0000";
       signal Timer: integer range 0 to 1023;
       signal Clk:   std_logic := '0';
       signal Datain: std_logic := '0';
    begin
     
       clk <= not clk after 500 us; -- This code NOT for synthesizing - only simulation
       -- simulates a frequency of 1kHz which used for the 1 second generation.
       
       Datain <= not Datain after 60 ms; -- This code NOT for synthesizing - only simulation
       -- simulation of input data.
      
       process( clk, Datain)
       begin
          -- This construction only for simulation - can't be synthesized
          if rising_edge( Datain) then
             TempCount <= TempCount +1;   -- Count the frequency.
          end if;
    
          -- one second timer functionality 
          if rising_edge( clk) then
             timer <= timer+1;
             if timer>999 then          -- Now 1 Second gone
                timer <= 0;             -- Init timer to next second count
                FreqCount <= TempCount; -- Remember the count 
                TempCount <= "0000";    -- Init for next count
             end if;
          end if;
       end process;        
       
    end Behavioral;
    Last edited: Dec 7, 2009
    jeppe, Dec 6, 2009
    #4
  5. johnnyjohn2009

    johnnyjohn2009

    Joined:
    Dec 3, 2009
    Messages:
    8
    Hi Jeppe,

    The code you posted is extremely interesting.. it has certainly given me some ideas to go away and experiment.

    There have been many discussions in VHDL books regarding unsynthesisable code for hardware implementation. However no author has explaining exactly why..

    I do plan to implement this on a Xilinx Spartan 3E board if I have time so I should make sure my code is synthesisable and not just for simulation.

    John
    johnnyjohn2009, Dec 8, 2009
    #5
  6. johnnyjohn2009

    jeppe

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    Messages:
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    Location:
    Denmark
    Hi John

    Its not that difficult to spot code which can't be synthesized.
    All VHDL code which depend on delays like Y <= Not AFTER ... or WAIT FOR xx NS will fail to synthesize.
    Your allowed to use FOR and WHILE loops if they generates COMBINATORIAL logic, but if you write "normal program code" which wait for something to happen will the synthesize process fail as well.

    In my code example must the 1 kHz come from an external source (and will proberly be 50 MHz)
    You must realize that a process normally only will allow one signal which depend on a rising_edge and hence must you "create" an extra rising edge detection for the Datain signal.
    This can be done with a two bit shiftregister which remember the actual and former value of the Datain signal - hence will "10" indicate a rising edge.

    Jeppe
    jeppe, Dec 9, 2009
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