Clock problem in Behavioural Program

[Ved P Singh]

Hello people,
PLease refer the connections and codes mentioned below.

Problem is that I am getting the output changed at rising edge as well
as falling edge of clock !!!
Though i have never mentioned about fallind edge anywhere, and have
used only rising edges only.

------------------CONNECTIONS-----------------------------------

The three codes given below are:


(1) counter with count values on port "Q_count"(acting as DAG for the
ROM)

(2) second is a ROM which is acting like a data provider and is giving
output at
port "Q".

(3) Third is a behavioural code which does frame forming(array
forming) in a particular manner

After compiling the 3 codes seperately,the connections between them
have to be like this

Q_count => ADDRESS -----between counter than ROM

Q => frame ----- between ROM and behavioural model

sig_ser_enc1 => output ------ Behavioural and output
port

---------------------------END CONNECTIONS-------------------------


----------------------START CODES--------------------
---------****************COUNTER **********************

library IEEE;
use IEEE.std_logic_1164.all;

entity counter_temp is
port (
CLK : in std_logic;
CLR : in std_logic;
Q_count : out std_logic_vector(3 downto 0)
);
end entity;

--}} End of automatically maintained section

library IEEE;
use IEEE.std_logic_unsigned.all;

architecture counter_arch of counter_temp is
signal TEMP_Q : std_logic_vector(3 downto 0);
begin

process(CLK)
begin
if rising_edge(CLK) then
if CLR = '1' then
TEMP_Q <= (others => '0');
else
TEMP_Q <= TEMP_Q + 1;
end if;
end if;
end process;

Q_count <= TEMP_Q;

end architecture;
------------------END COUNTER*****************



-----***************** ROM ******************



library IEEE;
use IEEE.std_logic_1164.all;

entity rom_1x16_data is
port (
ADDRESS : in std_logic_vector(3 downto 0);
Q : out std_Ulogic;
CLK : in std_logic;
CE : in std_logic
);
end entity;

--}} End of automatically maintained section

library IEEE;
use IEEE.std_logic_unsigned.all;

architecture rom_arch of rom_1x16_data is
begin

process(CLK)
begin
if rising_edge(CLK) then
if CE = '1' then
case (ADDRESS) is
when "0000" => Q <= '1'; -- 0
when "0001" => Q <= '1'; -- 1
when "0010" => Q <= '0'; -- 2
when "0011" => Q <= '1'; -- 3
when "0100" => Q <= '0'; -- 4
when "0101" => Q <= '1'; -- 5
when "0110" => Q <= '0'; -- 6
when "0111" => Q <= '1'; -- 7
when "1000" => Q <= '1'; -- 8
when "1001" => Q <= '0'; -- 9
when "1010" => Q <= '1'; -- A
when "1011" => Q <= '0'; -- B
when "1100" => Q <= '0'; -- C
when "1101" => Q <= '1'; -- D
when "1110" => Q <= '0'; -- E
when "1111" => Q <= '0'; -- F

when others => Q <= '0';
end case;
end if;
end if;

end process;
end architecture;


----*******************END ROM *************************



-------*********BEHAVIOURAL-------------------

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity Top_level_Encoder_Behav is
port(
frame : in STD_LOGIC;
clk : in STD_LOGIC;
reset : in STD_LOGIC;
sig_ser_enc1 : out std_logic
);
end Top_level_Encoder_Behav;


architecture Top_level_Encoder_Behav of Top_level_Encoder_Behav is

begin

p1: process(reset,clk)

variable fr_cache : std_logic_vector(15 downto 0);
VARIABLE fr_length :integer RANGE 0 TO 15;
variable tmp1 : integer RANGE 0 TO 13;
variable data14_enc1 : std_logic_vector(13 downto 0);
variable data_ser_enc1 : std_logic;
begin
if reset='1' then
fr_length:= 0;
fr_cache := "0000000000000000";
else if rising_edge(CLK) then
fr_cache(fr_length):= frame ;

if fr_length = 15 then
fr_length := 0;
else
fr_length:= fr_length +1;
end if;

end if;
end if;

data14_enc1(13 downto 0) := fr_cache(13 downto 0) ;
-------taking only 14bits out of 16bits


if tmp1 = 13 then
tmp1 := 0; ----converting paraller to serial
else
tmp1 := tmp1 + 1;
end if;

data_ser_enc1 := data14_enc1(tmp1) ;
sig_ser_enc1 <= data_ser_enc1;

end process ;

end Top_level_Encoder_Behav;


----------******END BEHAVIOURAL***************************


---THANKS IN ADVANCE

 

[Egbert Molenkamp]

Hello people,
PLease refer the connections and codes mentioned below.

Problem is that I am getting the output changed at rising edge as well
as falling edge of clock !!!
Though i have never mentioned about fallind edge anywhere, and have
used only rising edges only.

p1: process(reset,clk)

variable fr_cache : std_logic_vector(15 downto 0);
VARIABLE fr_length :integer RANGE 0 TO 15;
variable tmp1 : integer RANGE 0 TO 13;
variable data14_enc1 : std_logic_vector(13 downto 0);
variable data_ser_enc1 : std_logic;
begin
if reset='1' then
fr_length:= 0;
fr_cache := "0000000000000000";
else if rising_edge(CLK) then
fr_cache(fr_length):= frame ;

if fr_length = 15 then
fr_length := 0;
else
fr_length:= fr_length +1;
end if;

end if;
end if;

data14_enc1(13 downto 0) := fr_cache(13 downto 0) ;
-------taking only 14bits out of 16bits


if tmp1 = 13 then
tmp1 := 0; ----converting paraller to serial
else
tmp1 := tmp1 + 1;
end if;

data_ser_enc1 := data14_enc1(tmp1) ;
sig_ser_enc1 <= data_ser_enc1;

end process ;

end Top_level_Encoder_Behav;

This process has the following structure:

process(reset,clk)
...
begin
if reset='1' then
async reset actions
elsif rising-edge(clk) then
synchronous actions
end if;
HERE ARE THE PROBLEMS.
end process;

Notice that if reset='0' and clk changes from '1' to '0' the process is
executed and the code "HERE ARE THE PROBLEMS" is executed. Indeed on the
falling edge of the clock.Notice htat it can increment value tmp1 and this
it behaviour changes on the falling edge.

Egbert Molenkamp

 

[Mike Treseler]

This process has the following structure:
process(reset,clk)
..
begin
if reset='1' then
async reset actions
elsif rising-edge(clk) then
synchronous actions
end if;
HERE ARE THE PROBLEMS.
end process;

Notice that if reset='0' and clk changes from '1' to '0' the process is
executed and the code "HERE ARE THE PROBLEMS" is executed. Indeed on the
falling edge of the clock.

Excellent diagnosis.

Interesting. The procedure HERE_ARE_THE_PROBLEMS;
is executed on both edges of reset
and on both edges of clock.

Since it follows the /if/elsif/end if/ statement,
HERE_ARE_THE_PROBLEMS will have the last
word on variable and signal assignments.

Synthesizing logic using both clock
edges is not useful to me, but I
have played with a simple HERE_ARE_THE_PROBLEMS;
procedure consisting of a simple assignment.

my_reg_v <= my_port_pin;

This sims and synthesizes fine as a wire
to a port or architecture signal for
Mentor and Quartus tools.

This is not a recommendation.
Such assignments more properly belong
in the /elsif rising_edge(clk) clause.
But it is interesting because the
my_reg_v reset behavior is automatically
duplicated to the port without requiring
a separate assignment or generating
a duplicate register.


-- Mike Treseler

 

[Mike Treseler]

my_reg_v <= my_port_pin;

but he meant:

my_port_pin <= my_reg_v;



-- Mike Treseler

 

[Mike Treseler]

Here's an example of saving or wasting output
registers by matching or mixing reset schemes:

http://home.comcast.net/~mike_treseler/var_synth.vhd
http://home.comcast.net/~mike_treseler/var_synth.pdf

-- Mike Treseler