Renaud Pacalet said:
Jamie a écrit :
Well, a synchronous state machine is usually made of a synchronous state
register (with next state as data input, current state as data output, clock and
sync or async reset), a combinational circuit computing the next state from the
current state and the inputs and a combinational circuit computing the outputs
from the current state (and the inputs in case of a Meally machine). Usually
this leads to a single synchronous process modelling the state register or the
state register and the first combinational circuit plus one or more
combinational processes modelling the outputs computations. Usually the
sensivity list of the synchronous process contains only the clock and,
optionally, the asynchronous reset. So if you remove the clock you get an empty
list or the asynchronous reset, that is not much. Example with 3 processes:
type TSTATE is (S0, S1, S2);
signal STATE: TSTATE;
...
process(CLK, RSTN)
begin
if RSTN = '0' then
STATE <= S0;
elsif RISING_EDGE(CLK) then
case STATE is
when S0 => if IN0 = '1' then
STATE <= S1;
end if;
when S1 => STATE <= S2;
when S2 => if IN1 = '1' then
STATE <= S0;
end if;
end case;
end if;
end process;
OUT0 <= '1' when STATE = S0 else
'0';
OUT1<= '1' when STATE = S1 else
'0';
In this very simple example if you remove CLK from the sensivity list of the
synchronous process all you get is:
process(RSTN)
begin
if RSTN = '0' then
STATE <= S0;
elsif RISING_EDGE(CLK) then
case STATE is
when S0 => if IN0 = '1' then
STATE <= S1;
end if;
when S1 => STATE <= S2;
when S2 => if IN1 = '1' then
STATE <= S0;
end if;
end case;
end if;
end process;
I beleive most synthesizers will reject this with at least a bunch of warnings.
But if one does not then I can't imagine what it could synthesize. In case
StateCAD that I don't know puts every LHS signals in the sensivity list (some
tools do this, never understood why), after CLK removal you get:
process(RSTN, STATE, IN0, IN1)
begin
if RSTN = '0' then
STATE <= S0;
elsif RISING_EDGE(CLK) then
case STATE is
when S0 => if IN0 = '1' then
STATE <= S1;
end if;
when S1 => STATE <= S2;
when S2 => if IN1 = '1' then
STATE <= S0;
end if;
end case;
end if;
end process;
And I still can't imagine what could be synthesized from this. For my personal
culture could you give us your code before and after clock removal?
Best regards,
My code follows. The commented out lines of code are what I removed to
be free of the clock.
-- VHDL code created by Xilinx's StateCAD 6.1i
-- Mon Oct 20 13:05:15 2003
-- This VHDL code (for use with Xilinx XST) was generated using:
-- enumerated state assignment with structured code format.
-- Minimization is enabled, implied else is disabled,
-- and outputs are speed optimized.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
-- Finite State Machine to decode direction
-- of the HEDR-8000 OPTICAL SM ENCODER
-- ...00<->01<->11<->10...
ENTITY KDECODE IS
port (A,B: in std_logic;
--PORT (CLK,A,B,RESET: IN std_logic;
DBIT,UBIT : OUT std_logic);
attribute NOREDUCE: string;
END;
ARCHITECTURE BEHAVIOR OF KDECODE IS
TYPE type_sreg IS (S0,S1,S2,S3,S4,S5,S6,S7);
SIGNAL sreg, next_sreg : type_sreg;
SIGNAL next_DBIT,next_UBIT : std_logic;
attribute NOREDUCE of next_sreg: signal is "true";
BEGIN
process(next_sreg, next_DBIT, next_UBIT)
--PROCESS (CLK, RESET, next_sreg, next_DBIT, next_UBIT)
BEGIN
sreg <= next_sreg;
DBIT <= next_DBIT;
UBIT <= next_UBIT;
--IF ( RESET='1' ) THEN
-- sreg <= S0;
-- DBIT <= '0';
-- UBIT <= '0';
--ELSIF CLK='1' AND CLK'event THEN
-- sreg <= next_sreg;
-- DBIT <= next_DBIT;
-- UBIT <= next_UBIT;
--END IF;
END PROCESS;
PROCESS (sreg,A,B)
BEGIN
next_DBIT <= '0'; next_UBIT <= '0';
next_sreg<=S0;
CASE sreg IS
WHEN S0 =>
IF ( A='1' AND B='0' ) THEN
next_sreg<=S7;
next_UBIT<='0';
next_DBIT<='1';
END IF;
IF ( A='0' AND B='1' ) THEN
next_sreg<=S1;
next_DBIT<='0';
next_UBIT<='1';
END IF;
IF ( A='0' AND B='0' ) THEN
next_sreg<=S0;
next_DBIT<='0';
next_UBIT<='0';
END IF;
IF ( A='1' AND B='1' ) THEN
next_sreg<=S2;
next_DBIT<='0';
next_UBIT<='0';
END IF;
WHEN S1 =>
IF ( A='0' AND B='0' ) THEN
next_sreg<=S4;
next_DBIT<='1';
next_UBIT<='1';
END IF;
IF ( A='1' AND B='1' ) THEN
next_sreg<=S2;
next_DBIT<='0';
next_UBIT<='0';
END IF;
IF ( B='1' AND A='0' ) THEN
next_sreg<=S1;
next_DBIT<='0';
next_UBIT<='1';
END IF;
IF ( A='1' AND B='0' ) THEN
next_sreg<=S3;
next_DBIT<='0';
next_UBIT<='1';
END IF;
WHEN S2 =>
IF ( A='0' AND B='1' ) THEN
next_sreg<=S5;
next_UBIT<='0';
next_DBIT<='1';
END IF;
IF ( A='1' AND B='0' ) THEN
next_sreg<=S3;
next_DBIT<='0';
next_UBIT<='1';
END IF;
IF ( A='1' AND B='1' ) THEN
next_sreg<=S2;
next_DBIT<='0';
next_UBIT<='0';
END IF;
IF ( A='0' AND B='0' ) THEN
next_sreg<=S0;
next_DBIT<='0';
next_UBIT<='0';
END IF;
WHEN S3 =>
IF ( A='1' AND B='1' ) THEN
next_sreg<=S6;
next_DBIT<='1';
next_UBIT<='1';
END IF;
IF ( A='0' AND B='0' ) THEN
next_sreg<=S0;
next_DBIT<='0';
next_UBIT<='0';
END IF;
IF ( B='0' AND A='1' ) THEN
next_sreg<=S3;
next_DBIT<='0';
next_UBIT<='1';
END IF;
IF ( A='0' AND B='1' ) THEN
next_sreg<=S1;
next_DBIT<='0';
next_UBIT<='1';
END IF;
WHEN S4 =>
IF ( A='1' AND B='0' ) THEN
next_sreg<=S3;
next_DBIT<='0';
next_UBIT<='1';
END IF;
IF ( A='0' AND B='1' ) THEN
next_sreg<=S5;
next_UBIT<='0';
next_DBIT<='1';
END IF;
IF ( A='0' AND B='0' ) THEN
next_sreg<=S4;
next_DBIT<='1';
next_UBIT<='1';
END IF;
IF ( A='1' AND B='1' ) THEN
next_sreg<=S6;
next_DBIT<='1';
next_UBIT<='1';
END IF;
WHEN S5 =>
IF ( A='0' AND B='0' ) THEN
next_sreg<=S0;
next_DBIT<='0';
next_UBIT<='0';
END IF;
IF ( A='1' AND B='1' ) THEN
next_sreg<=S6;
next_DBIT<='1';
next_UBIT<='1';
END IF;
IF ( B='1' AND A='0' ) THEN
next_sreg<=S5;
next_UBIT<='0';
next_DBIT<='1';
END IF;
IF ( A='1' AND B='0' ) THEN
next_sreg<=S7;
next_UBIT<='0';
next_DBIT<='1';
END IF;
WHEN S6 =>
IF ( A='0' AND B='0' ) THEN
next_sreg<=S4;
next_DBIT<='1';
next_UBIT<='1';
END IF;
IF ( A='0' AND B='1' ) THEN
next_sreg<=S1;
next_DBIT<='0';
next_UBIT<='1';
END IF;
IF ( A='1' AND B='0' ) THEN
next_sreg<=S7;
next_UBIT<='0';
next_DBIT<='1';
END IF;
IF ( A='1' AND B='1' ) THEN
next_sreg<=S6;
next_DBIT<='1';
next_UBIT<='1';
END IF;
WHEN S7 =>
IF ( A='0' AND B='1' ) THEN
next_sreg<=S5;
next_UBIT<='0';
next_DBIT<='1';
END IF;
IF ( A='1' AND B='1' ) THEN
next_sreg<=S2;
next_DBIT<='0';
next_UBIT<='0';
END IF;
IF ( A='0' AND B='0' ) THEN
next_sreg<=S4;
next_DBIT<='1';
next_UBIT<='1';
END IF;
IF ( B='0' AND A='1' ) THEN
next_sreg<=S7;
next_UBIT<='0';
next_DBIT<='1';
END IF;
WHEN OTHERS =>
END CASE;
END PROCESS;
END BEHAVIOR;