Compare pairs of bits between two slv's ?

Discussion in 'VHDL' started by Tony Benham, Oct 31, 2003.

  1. Tony Benham

    Tony Benham Guest

    I've been puzzling how I can write concise vhdl that will basically set a
    bit if any pair of bits in two slv's are both hi ?
    A sort of pseudo code for what I want to do is as follows
    mask : std_logic_vector(7 downto 0) ;
    trig : std_logic_vector(7 downto 0) ;
    set : std_logic;

    set <= '0' ;
    for i in 0 to 7
    If mask(i) AND trig(i) = '1'
    set <= '1' ;
    end if ;
    end for ;

    In english, if any pair of bits in the two slv's are both hi, the set will
    be set to one, else zero

    I thought about using For-Generate, but I'm puzzled how to apply for this
    case ?

    Regards
    Tony
    Tony Benham, Oct 31, 2003
    #1
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  2. S1 <= '0' when (Mask and Trig) = 0 else '1';
    Valentin Tihomirov, Oct 31, 2003
    #2
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  3. Tony Benham

    David Bishop Guest

    This is why we are thinking of putting vector reduction into
    VHDL.

    Try this:

    set := or_reduce (mask and trig);

    You will find a copy of "or_reduce" at:
    http://www.vhdl.org/vhdlsynth/

    This is functionality we also plan to add in 1164 as well.

    Tony Benham wrote:

    > I've been puzzling how I can write concise vhdl that will basically set a
    > bit if any pair of bits in two slv's are both hi ?
    > A sort of pseudo code for what I want to do is as follows
    > mask : std_logic_vector(7 downto 0) ;
    > trig : std_logic_vector(7 downto 0) ;
    > set : std_logic;
    >
    > set <= '0' ;
    > for i in 0 to 7
    > If mask(i) AND trig(i) = '1'
    > set <= '1' ;
    > end if ;
    > end for ;
    >
    > In english, if any pair of bits in the two slv's are both hi, the set will
    > be set to one, else zero
    >
    > I thought about using For-Generate, but I'm puzzled how to apply for this
    > case ?
    >
    > Regards
    > Tony
    >
    >


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    For VHDL/Synthesis info: http://www.vhdl.org/vhdlsynth _/___\_
    All standard disclaimers apply. [_______]
    David Bishop, Nov 1, 2003
    #3
  4. I've just reading an answer to my qustion here
    http://www.eda.org/comp.lang.vhdl/FAQ1.html
    and encountered Reduction section.

    -- this concurrent assignment performs an "or"
    -- reduction on "a_vec"
    a <= '0' when (a_vec = (a_vec'range => '0')) else '1';

    -- while this calculates an "and" reduction
    a <= '1' when (a_vec = (a_vec'range => '1')) else '0';

    Read there about reducing vectors containing 'X' values.
    Valentin Tihomirov, Nov 2, 2003
    #4
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