Component and desing vision?

Discussion in 'VHDL' started by kyrpa83, Oct 14, 2007.

  1. kyrpa83

    kyrpa83

    Joined:
    Oct 14, 2007
    Messages:
    3
    Hi!

    I am not sure about right words in vhdl but i hope you understand what i am trying to ask. I am writing and compiling hierarchical system in modelsim( i mean that i have included all-ready compiled components to my top level vhdl-code).Every thing works fine. My next step in my project is to compile the design into ASIC and then create a gatelevel testbench using design vision. The created testbench is then again compiled using modelsim but there will be problems when i try to compile it. The compiler doesnt found different componont instances which are created from the same "mother component". I have tested that if i have only one component instance every thing will work fine.

    My question: What should i do to get all component instances works??
    The problem is probably in this line in my top-level code( for all: top_rtl_synt use ENTITY WORK.top_rtl_synt(RTL); ) (i have tested that in modelsim i can create different instances from the same mother component without or with this line. But both wont work when i compile that testbench from those codes, because i doesnt find those instances
    kyrpa83, Oct 14, 2007
    #1
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